专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08788742B2 Using an attribute of a write request to determine where to cache data in a storage system having multiple caches including non-volatile storage cache in a sequential access storage device 有权
公开(公告)号：US08788742B2
公开(公告)日：2014-07-22
申请号：US13113949
申请日：2011-05-23
申请人： Michael T. Benhase , Binny S. Gill , Lokesh M. Gupta , Matthew J. Kalos
发明人： Michael T. Benhase , Binny S. Gill , Lokesh M. Gupta , Matthew J. Kalos
IPC分类号： G06F12/00
CPC分类号： G06F12/0866 , G06F12/123
摘要： Provided are a computer program product, system, and method for using an attribute of a write request to determine where to cache data in a storage system having multiple caches including non-volatile storage cache in a sequential access storage device. Received modified tracks are cached in the non-volatile storage device integrated with the sequential access storage device in response to determining to cache the modified tracks. A write request having modified tracks is received. A determination is made as to whether an attribute of the received write request satisfies a condition. The received modified tracks for the write request are cached in the non-volatile storage device in response to determining that the determined attribute does not satisfy the condition. A destage request is added to a request queue for the received write request having the determined attribute not satisfying the condition.

2. 发明授权

US08667180B2 Compression on thin provisioned volumes using extent based mapping 失效
标题翻译：使用基于范围的映射压缩精简配置卷
公开(公告)号：US08667180B2
公开(公告)日：2014-03-04
申请号：US13531925
申请日：2012-06-25
申请人： Michael T. Benhase , Binny S. Gill , Lokesh M. Gupta , Matthew J. Kalos , Gail A. Spear
发明人： Michael T. Benhase , Binny S. Gill , Lokesh M. Gupta , Matthew J. Kalos , Gail A. Spear
IPC分类号： G06F15/16
CPC分类号： G06F3/064 , G06F3/0608 , G06F3/0613 , G06F3/067 , G06F12/0804 , G06F12/0868 , G06F2212/401
摘要： For facilitating data compression, a set of logical extents, each having compressed logical tracks of data, is mapped to a head physical extent and, if the head physical extent is determined to have been filled, to at least one overflow extent having spatial proximity to the head physical extent. Pursuant to at least one subsequent write operation and destage operation, the at least one subsequent write operation and destage operation determined to be associated with the head physical extent, the write operation is mapped to one of the head physical extent, the at least one overflow extent, and an additional extent having spatial proximity to the at least one overflow extent.
摘要翻译：为了便于数据压缩，将具有压缩的数据的逻辑轨迹的一组逻辑盘区映射到头部物理范围，并且如果将头部物理范围确定为已经被填充到至少一个具有空间接近的溢出范围头部物理范围。根据至少一个随后的写入操作和终止操作，所述至少一个随后的写入操作和后退操作被确定为与所述头部物理范围相关联，所述写入操作被映射到所述头部物理范围中的一个，所述至少一个溢出并且具有与至少一个溢出范围的空间接近的附加程度。

3. 发明授权

US08656088B2 Optimized flash based cache memory 失效
标题翻译：优化基于闪存的高速缓存
公开(公告)号：US08656088B2
公开(公告)日：2014-02-18
申请号：US13112894
申请日：2011-05-20
申请人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Eyal Lotem , Venu G. Nayar , Assaf Nitzan , Edi Shmueli , Daniel F. Smith
发明人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Eyal Lotem , Venu G. Nayar , Assaf Nitzan , Edi Shmueli , Daniel F. Smith
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/0246 , G06F12/0866 , G06F12/0897 , G06F2212/1036 , G06F2212/222
摘要： Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold.
摘要翻译：本发明的实施例涉及对闪存设备的限制访问。闪存设备是包括闪存设备和第二存储设备的存储系统的一部分。节流由闪存设备外部的逻辑执行，并且包括响应于闪存设备的估计剩余寿命来计算节流因子。确定节流因子是否超过阈值。响应于确定节流因子不超过阈值，将数据写入闪存设备。响应于确定节流因子超过阈值，将数据写入第二存储器件。

4. 发明授权

US08631190B2 Prefetching data tracks and parity data to use for destaging updated tracks 失效
标题翻译：预取数据轨道和奇偶校验数据以用于降级更新的轨道
公开(公告)号：US08631190B2
公开(公告)日：2014-01-14
申请号：US13189285
申请日：2011-07-22
申请人： Michael T. Benhase , Binny S. Gill , Lokesh M. Gupta , James L. Hafner
发明人： Michael T. Benhase , Binny S. Gill , Lokesh M. Gupta , James L. Hafner
IPC分类号： G06F13/10
CPC分类号： G06F12/0868 , G06F12/0862 , G06F12/0897
摘要： Provided are a computer program product, system, and method for prefetching data tracks and parity data to use for destaging updated tracks. A write request is received including at least one updated track to the group of tracks. The at least one updated track is stored in a first cache device. A prefetch request is sent to the at least one sequential access storage device to prefetch tracks in the group of tracks to a second cache device. A read request is generated to read the prefetch tracks following the sending of the prefetch request. The read prefetch tracks returned to the read request from the second cache device are stored in the first cache device. New parity data is calculated from the at least one updated track and the read prefetch tracks.
摘要翻译：提供了一种用于预取数据轨道和奇偶校验数据以用于降级更新的轨道的计算机程序产品，系统和方法。接收包括至少一个更新的轨道到轨道组的写入请求。所述至少一个更新的轨道存储在第一高速缓存设备中。预取请求被发送到至少一个顺序访问存储设备以将轨道组中的轨道预取到第二高速缓存设备。在发送预取请求之后，生成读取请求以读取预取轨迹。从第二高速缓存设备返回到读取请求的读取预取轨迹存储在第一高速缓存设备中。从所述至少一个更新的轨道和读取的预取轨迹计算新的奇偶校验数据。

5. 发明授权

US08386714B2 Reducing write amplification in a cache with flash memory used as a write cache 有权
标题翻译：在缓存中减少写入放大，闪存用作写缓存
公开(公告)号：US08386714B2
公开(公告)日：2013-02-26
申请号：US12826499
申请日：2010-06-29
申请人： Wendy A. Belluomini , Binny S. Gill , Michael A. Ko
发明人： Wendy A. Belluomini , Binny S. Gill , Michael A. Ko
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0804 , G06F12/0868 , G06F2212/2022 , G06F2212/282 , G06F2212/461
摘要： Embodiments of the invention are directed to reducing write amplification in a cache with flash memory used as a write cache. An embodiment of the invention includes partitioning at least one flash memory device in the cache into a plurality of logical partitions. Each of the plurality of logical partitions is a logical subdivision of one of the at least one flash memory device and comprises a plurality of memory pages. Data are buffered in a buffer. The data includes data to be cached, and data to be destaged from the cache to a storage subsystem. Data to be cached are written from the buffer to the at least one flash memory device. A processor coupled to the buffer is provided with access to the data written to the at least one flash memory device from the buffer, and a location of the data written to the at least one flash memory device within the plurality of logical partitions. The data written to the at least one flash memory device are destaged from the buffer to the storage subsystem.
摘要翻译：本发明的实施例旨在减少用作写入高速缓存的闪存的高速缓存中的写入放大。本发明的实施例包括将高速缓存中的至少一个闪存设备划分成多个逻辑分区。多个逻辑分区中的每一个是至少一个闪速存储器设备之一的逻辑细分，并且包括多个存储器页。数据被缓冲在缓冲区中。数据包括要缓存的数据以及要从高速缓存迁移到存储子系统的数据。要缓存的数据从缓冲器写入至少一个闪速存储器件。耦合到缓冲器的处理器提供对从缓冲器写入至少一个闪速存储器设备的数据的访问，以及写入多个逻辑分区内的至少一个闪存设备的数据的位置。写入至少一个闪存设备的数据从缓冲器中迁移到存储子系统。

6. 发明申请

US20130024624A1 PREFETCHING TRACKS USING MULTIPLE CACHES 有权
公开(公告)号：US20130024624A1
公开(公告)日：2013-01-24
申请号：US13189271
申请日：2011-07-22
申请人： Michael T. Benhase , Binny S. Gill , Lokesh M. Gupta , James L. Hafner
发明人： Michael T. Benhase , Binny S. Gill , Lokesh M. Gupta , James L. Hafner
IPC分类号： G06F12/12
CPC分类号： G06F12/12 , G06F12/0862
摘要： Provided are a computer program product, sequential access storage device, and method for managing data in a sequential access storage device receiving read requests and write requests from a system with respect to tracks stored in a sequential access storage medium. A prefetch request indicates prefetch tracks in the sequential access storage medium to read from the sequential access storage medium. The accessed prefetch tracks are cached in a non-volatile storage device integrated with the sequential access storage device, wherein the non-volatile storage device is a faster access device than the sequential access storage medium. A read request is received for the prefetch tracks following the caching of the prefetch tracks, wherein the prefetch request is designated to be processed at a lower priority than the read request with respect to the sequential access storage medium. The prefetch tracks are returned from the non-volatile storage device to the read request.

7. 发明申请

US20120297127A1 OPTIMIZED FLASH BASED CACHE MEMORY 失效
公开(公告)号：US20120297127A1
公开(公告)日：2012-11-22
申请号：US13553194
申请日：2012-07-19
申请人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Assaf Nitzan , Eyal Lotem , Venu G. Nayar , Edi Shmueli , Daniel F. Smith
发明人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Assaf Nitzan , Eyal Lotem , Venu G. Nayar , Edi Shmueli , Daniel F. Smith
IPC分类号： G06F12/02
CPC分类号： G06F12/0888 , G06F12/0246 , G06F12/0866 , G06F12/0897 , G06F2212/1036 , G06F2212/222
摘要： Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold.

8. 发明申请

US20120297113A1 OPTIMIZED FLASH BASED CACHE MEMORY 失效
标题翻译：优化的基于闪存的高速缓存存储器
公开(公告)号：US20120297113A1
公开(公告)日：2012-11-22
申请号：US13112894
申请日：2011-05-20
申请人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Assaf Nitzan , Eyal Lotem , Venu G. Nayar , Edi Shmueli , Daniel F. Smith
发明人： Wendy A. Belluomini , Binny S. Gill , James L. Hafner , Steven R. Hetzler , Assaf Nitzan , Eyal Lotem , Venu G. Nayar , Edi Shmueli , Daniel F. Smith
IPC分类号： G06F12/02
CPC分类号： G06F12/0888 , G06F12/0246 , G06F12/0866 , G06F12/0897 , G06F2212/1036 , G06F2212/222
摘要： Embodiments of the invention relate to throttling accesses to a flash memory device. The flash memory device is part of a storage system that includes the flash memory device and a second memory device. The throttling is performed by logic that is external to the flash memory device and includes calculating a throttling factor responsive to an estimated remaining lifespan of the flash memory device. It is determined whether the throttling factor exceeds a threshold. Data is written to the flash memory device in response to determining that the throttling factor does not exceed the threshold. Data is written to the second memory device in response to determining that the throttling factor exceeds the threshold.
摘要翻译：本发明的实施例涉及对闪存设备的限制访问。闪存设备是包括闪存设备和第二存储设备的存储系统的一部分。节流由闪存设备外部的逻辑执行，并且包括响应于闪存设备的估计剩余寿命来计算节流因子。确定节流因子是否超过阈值。响应于确定节流因子不超过阈值，将数据写入闪存设备。响应于确定节流因子超过阈值，将数据写入第二存储器件。

9. 发明申请

US20120254544A1 SYSTEMS AND METHODS FOR MANAGING DESTAGE CONFLICTS 失效
标题翻译：用于管理灭绝冲突的系统和方法
公开(公告)号：US20120254544A1
公开(公告)日：2012-10-04
申请号：US13493794
申请日：2012-06-11
申请人： Brent C. BEARDSLEY , Michael T. BENHASE , Binny S. GILL , Lokesh M. GUPTA , Sonny E. WILLIAMS
发明人： Brent C. BEARDSLEY , Michael T. BENHASE , Binny S. GILL , Lokesh M. GUPTA , Sonny E. WILLIAMS
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/023 , G06F12/0804 , G06F12/0866
摘要： A system includes a cache partitioned into multiple ranks configured to store multiple storage tracks and a processor coupled to the cache. The processor is configured to perform the following method. One method includes allocating an amount of storage space in the cache to each rank and monitoring a current amount of storage space used by each rank with respect to the amount of storage space allocated to each respective rank. The method further includes destaging storage tracks from each rank until the current amount of storage space used by each respective rank is equal to a predetermined minimum amount of storage space with respect to the amount of storage space allocated to each rank.
摘要翻译：系统包括被分配成多个级别的缓存，其被配置为存储多个存储轨道，以及耦合到高速缓存的处理器。处理器配置为执行以下方法。一种方法包括将高速缓存中的存储空间量分配给每个等级，并且针对分配给每个相应等级的存储空间量来监视每个等级使用的当前存储空间量。该方法还包括对每个等级的存储轨道进行降级，直到每个相应等级使用的当前存储空间量相对于分配给每个等级的存储空间量等于预定的最小存储空间量。

10. 发明申请

US20120198148A1 ADAPTIVE PRESTAGING IN A STORAGE CONTROLLER 有权
标题翻译：存储控制器中的自适应PRISTAGING
公开(公告)号：US20120198148A1
公开(公告)日：2012-08-02
申请号：US13018305
申请日：2011-01-31
申请人： Michael T. Benhase , Nedlaya Y. Francisco , Binny S. Gill , Lokesh M. Gupta , Suguang Li
发明人： Michael T. Benhase , Nedlaya Y. Francisco , Binny S. Gill , Lokesh M. Gupta , Suguang Li
IPC分类号： G06F12/08
CPC分类号： G06F12/0246 , G06F12/0862 , G06F12/0866 , G06F12/0868
摘要： In one aspect of the present description, at least one of the value of a prestage trigger and the value of the prestage amount, may be modified as a function of the drive speed of the storage drive from which the units of read data are prestaged into a cache memory. Thus, cache prestaging operations in accordance with another aspect of the present description may take into account storage devices of varying speeds and bandwidths for purposes of modifying a prestage trigger and the prestage amount. Still further, a cache prestaging operation in accordance with further aspects may decrease one or both of the prestage trigger and the prestage amount as a function of the drive speed in circumstances such as a cache miss which may have resulted from prestaged tracks being demoted before they are used. Conversely, a cache prestaging operation in accordance with another aspect may increase one or both of the prestage trigger and the prestage amount as a function of the drive speed in circumstances such as a cache miss which may have resulted from waiting for a stage to complete. In yet another aspect, the prestage trigger may not be limited by the prestage amount. Instead, the pre-stage trigger may be permitted to expand as conditions warrant it by prestaging additional tracks and thereby effectively increasing the potential range for the prestage trigger. Other features and aspects may be realized, depending upon the particular application.
摘要翻译：在本说明书的一个方面，可以根据存储驱动器的驱动速度来修改预置触发器的值和预置量的值中的至少一个，读取数据的单元从该驱动速度被预先存储缓存内存因此，根据本说明书的另一方面的高速缓存预存操作可以考虑到变化速度和带宽的存储设备，以便修改预置触发和预置量。此外，根据其他方面的高速缓存预存操作可以在诸如高速缓存未命中的情况下降低前置触发和预置量中的一个或两个作为驱动速度的函数，这可能是由于在它们之前被分级的轨道被降级被使用。相反，根据另一方面的高速缓存预存操作可以在可能由于等待阶段完成而导致的诸如高速缓存未命中的情况下，增加作为驱动速度的函数的预置触发和预置量的一个或两个。在另一方面，前置触发器可以不受前置量的限制。相反，可以通过预先附加轨道的条件来允许前级触发来扩展，从而有效地增加了前置触发的潜在范围。可以根据具体应用实现其它特征和方面。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式