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1. 发明申请

US20150331981A1 Timing Verification of an Integrated Circuit 有权
标题翻译：集成电路的定时验证
公开(公告)号：US20150331981A1
公开(公告)日：2015-11-19
申请号：US14280056
申请日：2014-05-16
申请人： Brian J. Mulvaney
发明人： Brian J. Mulvaney
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036 , G06F17/5072 , G06F17/5077 , G06F2217/84
摘要： This disclosure describes a design tool that verifies timing of an integrated circuit design by partitioning the integrated circuit design's gate-level netlist into target cell partition netlists and performs transistor-level circuit simulation on each target cell partition netlist. The design tool performs a back tracing procedure on each target sequential cell to define the target cell partition netlists. The design tool then identifies timing modes that enable valid logical paths through the target cell partition netlists from source sequential cells to the target sequential cells. In turn, the design tool performs transistor-level circuit simulation (e.g., SPICE simulations) on each target cell partition netlist to check for timing violations based upon the timing modes. In one embodiment, the design tool includes clock tree delay information, power supply variations, or routing parasitic information in the simulations to achieve improved timing analysis accuracy compared with traditional static timing analysis or timing optimization.
摘要翻译：本公开描述了一种设计工具，其通过将集成电路设计的门级网表分成目标单元分区网表来验证集成电路设计的时序，并在每个目标单元分区网表上执行晶体管级电路仿真。设计工具对每个目标顺序单元执行后跟踪程序，以定义目标单元格分区网表。然后，设计工具识别定时模式，该定时模式使得能够通过源序列单元到目标顺序单元的目标单元分区网表的有效逻辑路径。反过来，设计工具在每个目标单元分区网表上执行晶体管级电路仿真（例如，SPICE仿真），以基于定时模式检查定时违规。在一个实施例中，与传统的静态时序分析或定时优化相比，设计工具包括模拟中的时钟树延迟信息，电源变化或路由寄生信息，以实现改进的时序分析精度。

2. 发明授权

US5799172A Method of simulating an integrated circuit 失效
标题翻译：模拟集成电路的方法
公开(公告)号：US5799172A
公开(公告)日：1998-08-25
申请号：US711638
申请日：1996-09-10
申请人： Kiran Kumar Gullapalli , Brian J. Mulvaney , Steven D. Hamm , Steven R. Beckerich
发明人： Kiran Kumar Gullapalli , Brian J. Mulvaney , Steven D. Hamm , Steven R. Beckerich
IPC分类号： G06F17/50 , G06G7/48
CPC分类号： G06F17/5036
摘要： A method and apparatus for simulating the design of an integrated circuit uses a processor (200). The processor (200) executes a simulator (540) from memory (280) to exercise a model (544). The data points (15-27) of an output signal are stored in a history data file (542). The techniques used to generate each of the data points (15-27) are also stored in the history data in file (542). The history data are then used to generate a converted output signal that has a uniform time scale. If the converted output signal requires the generation of a desired data point, then the approximation technique used to generate the following data point stored in the history data (542) is used.
摘要翻译：用于模拟集成电路的设计的方法和装置使用处理器（200）。处理器（200）从存储器（280）执行模拟器（540）以锻炼模型（544）。输出信号的数据点（15-27）存储在历史数据文件（542）中。用于生成每个数据点（15-27）的技术也被存储在文件（542）中的历史数据中。历史数据然后用于产生具有均匀时间尺度的转换的输出信号。如果转换的输出信号需要生成所需的数据点，则使用用于生成存储在历史数据（542）中的以下数据点的近似技术。

3. 发明授权

US09218440B2 Timing verification of an integrated circuit 有权
标题翻译：集成电路的定时验证
公开(公告)号：US09218440B2
公开(公告)日：2015-12-22
申请号：US14280056
申请日：2014-05-16
申请人： Brian J. Mulvaney
发明人： Brian J. Mulvaney
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036 , G06F17/5072 , G06F17/5077 , G06F2217/84
摘要： This disclosure describes a design tool that verifies timing of an integrated circuit design by partitioning the integrated circuit design's gate-level netlist into target cell partition netlists and performs transistor-level circuit simulation on each target cell partition netlist. The design tool performs a back tracing procedure on each target sequential cell to define the target cell partition netlists. The design tool then identifies timing modes that enable valid logical paths through the target cell partition netlists from source sequential cells to the target sequential cells. In turn, the design tool performs transistor-level circuit simulation (e.g., SPICE simulations) on each target cell partition netlist to check for timing violations based upon the timing modes. In one embodiment, the design tool includes clock tree delay information, power supply variations, or routing parasitic information in the simulations to achieve improved timing analysis accuracy compared with traditional static timing analysis or timing optimization.
摘要翻译：本公开描述了一种设计工具，其通过将集成电路设计的门级网表分成目标单元分区网表来验证集成电路设计的时序，并在每个目标单元分区网表上执行晶体管级电路仿真。设计工具对每个目标顺序单元执行后跟踪程序，以定义目标单元格分区网表。然后，设计工具识别定时模式，该定时模式使得能够通过源序列单元到目标顺序单元的目标单元分区网表的有效逻辑路径。反过来，设计工具在每个目标单元分区网表上执行晶体管级电路仿真（例如，SPICE仿真），以基于定时模式检查定时违规。在一个实施例中，与传统的静态时序分析或定时优化相比，设计工具包括模拟中的时钟树延迟信息，电源变化或路由寄生信息，以实现改进的时序分析精度。

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