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1. 发明授权

US07533236B1 Off-chip out of order memory allocation for a unified shader 有权
标题翻译：针对统一着色器的片外乱码内存分配
公开(公告)号：US07533236B1
公开(公告)日：2009-05-12
申请号：US11382888
申请日：2006-05-11
申请人： Bryon S. Nordquist
发明人： Bryon S. Nordquist
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F12/023 , G06F9/5016 , G06F2209/5011
摘要： Systems and methods for dynamically allocating memory for thread processing may reduce memory requirements while maintaining thread processing parallelism. A memory pool is allocated to store data for processing multiple threads that does not need to be large enough to dedicate a fixed size portion of the memory pool to each thread that may be processed in parallel. Fixed size portions of the memory pool are dynamically allocated and deallocated to each processing thread. Different fixed size portions may be used for different types of threads to allow greater thread parallelism compared with a system that requires allocating a single fixed portion of the memory pool to each thread. The memory pool may be shared between all of the thread types or divided to provide separate memory pools dedicated to each particular thread type.
摘要翻译：用于动态分配用于线程处理的存储器的系统和方法可以在维持线程处理并行性的同时减少内存需求。分配内存池以存储用于处理多个线程的数据，该线程不需要足够大以将内存池的固定大小部分专用于可并行处理的每个线程。内存池的固定大小部分被动态分配并释放到每个处理线程。不同的固定大小部分可以用于不同类型的线程，以允许与需要向每个线程分配存储器池的单个固定部分的系统相比更大的线程并行性。内存池可以在所有线程类型之间共享，也可以划分为专用于每个特定线程类型的独立内存池。

2. 发明授权

US07404059B1 Parallel copying scheme for creating multiple versions of state information 有权
标题翻译：用于创建多个版本的状态信息的并行复制方案
公开(公告)号：US07404059B1
公开(公告)日：2008-07-22
申请号：US11296894
申请日：2005-12-07
申请人： Bryon S. Nordquist
发明人： Bryon S. Nordquist
IPC分类号： G06F12/00
CPC分类号： G06F9/3851 , G06F9/462 , G06T15/005
摘要： State information in a processor is managed using a lookup table that has multiple memory circuits, each with multiple entries. Items of state information belonging to a first state version are stored in a first group of the entries, with each entry in the first group being in a different one of the memory circuits. To create an updated state version, the items of state information are copied in parallel from the first group of entries to a second group of entries, with each entry in the second group is in a different one of the memory circuits. The copy in the second group of the item being updated is then replaced with the updated value.
摘要翻译：使用具有多个存储器电路的查找表来管理处理器中的状态信息，每个存储器电路具有多个条目。属于第一状态版本的状态信息的项目被存储在第一组条目中，第一组中的每个条目都在不同的存储器电路中。为了创建更新的状态版本，状态信息项从第一组条目并行地复制到第二组条目，其中第二组中的每个条目都在不同的存储器电路中。随后更新的项目的第二组中的副本将被替换为更新的值。

3. 发明授权

US08081184B1 Pixel shader program thread assembly 有权
标题翻译：像素着色器程序线程程序集
公开(公告)号：US08081184B1
公开(公告)日：2011-12-20
申请号：US11381987
申请日：2006-05-05
申请人： Bryon S. Nordquist
发明人： Bryon S. Nordquist
IPC分类号： G06T15/50
CPC分类号： G06T15/005
摘要： Systems and methods for assembling pixel shader program threads for execution based on resource limitations of a multithreaded processor may improve processing throughput. Pixels to be processed by the pixel shader program are assembled into a launch group for processing by the multithreaded processor as multiple shader program threads. The pixels are assembled based on parameter storage resource limitations of the multithreaded processor so that common parameters shared by multiple pixels are not stored separately for each pixel. Therefore, the limited parameter storage resources are efficiently used, allowing more shader program threads to execute simultaneously.
摘要翻译：基于多线程处理器的资源限制来组合用于执行的像素着色器程序线程的系统和方法可以提高处理吞吐量。由像素着色器程序处理的像素被组装成发射组，以被多线程处理器处理为多个着色器程序线程。基于多线程处理器的参数存储资源限制来组装像素，使得由多个像素共享的公共参数不是针对每个像素单独存储。因此，有限参数存储资源被有效地使用，允许更多的着色器程序线程同时执行。

4. 发明授权

US08074224B1 Managing state information for a multi-threaded processor 有权
标题翻译：管理多线程处理器的状态信息
公开(公告)号：US08074224B1
公开(公告)日：2011-12-06
申请号：US11311963
申请日：2005-12-19
申请人： Bryon S. Nordquist , Brett W. Coon
发明人： Bryon S. Nordquist , Brett W. Coon
IPC分类号： G06F9/46 , G06F9/40 , G06F15/76
CPC分类号： G06F9/52 , G06F9/3012 , G06F9/30123 , G06F9/3851 , G06F9/3853 , G06F9/3887 , G06T1/20
摘要： Embodiments of the present invention facilitate dynamically adapting to state information changes in a graphics processing environment. In one embodiment, a master register holds state information corresponding to units of work (threads) to be performed. The state information in the master register is copied to a per-group state register when a group of threads is to be launched. The per-group state register is coupled to processing engines configured to process the threads, so that the processing engines read state information from the per-group state register rather than the master register. In another embodiment, a number of master registers may be used to store state information for different types of threads.
摘要翻译：本发明的实施例有助于动态地适应图形处理环境中的状态信息变化。在一个实施例中，主寄存器保存对应于要执行的工作单元（线程）的状态信息。当一组线程要启动时，主寄存器中的状态信息被复制到每组状态寄存器。每组状态寄存器被耦合到配置成处理线程的处理引擎，使得处理引擎从每组状态寄存器而不是主寄存器读取状态信息。在另一个实施例中，可以使用多个主寄存器来存储不同类型的线程的状态信息。

5. 发明授权

US08407443B1 Off-chip out of order memory allocation for a unified shader 有权
公开(公告)号：US08407443B1
公开(公告)日：2013-03-26
申请号：US12434422
申请日：2009-05-01
申请人： Bryon S. Nordquist
发明人： Bryon S. Nordquist
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/023 , G06F9/5016 , G06F2209/5011
摘要： Systems and methods for dynamically allocating memory for thread processing may reduce memory requirements while maintaining thread processing parallelism. A memory pool is allocated to store data for processing multiple threads that does not need to be large enough to dedicate a fixed size portion of the memory pool to each thread that may be processed in parallel. Fixed size portions of the memory pool are dynamically allocated and deallocated to each processing thread. Different fixed size portions may be used for different types of threads to allow greater thread parallelism compared with a system that requires allocating a single fixed portion of the memory pool to each thread. The memory pool may be shared between all of the thread types or divided to provide separate memory pools dedicated to each particular thread type.

6. 发明授权

US08095829B1 Soldier-on mode to control processor error handling behavior 有权
标题翻译：士兵启动模式来控制处理器错误处理行为
公开(公告)号：US08095829B1
公开(公告)日：2012-01-10
申请号：US11934730
申请日：2007-11-02
申请人： Brett W. Coon , Bryon S. Nordquist
发明人： Brett W. Coon , Bryon S. Nordquist
IPC分类号： G06F11/00 , G06F11/07
CPC分类号： G06F11/0721 , G06F11/0715 , G06F11/0772 , G06F11/0793
摘要： A global processor operating mode is used select whether a processor stops processing when an error is detected or ignores the error and continues processing while overriding values as needed to recover from the error. When a soldier-on mode is enabled the system attempts to recover from the error while also recording the error state of the first error in on-chip registers for later analysis. When the soldier-on mode is not enabled and an error occurs, the system stops processing and the error is reported up to the operating system.
摘要翻译：使用全局处理器操作模式，选择当检测到错误时处理器是否停止处理，或者忽略错误，并根据需要重新排列值，以便从错误中恢复。当启用士兵启动模式时，系统会尝试从错误中恢复，同时在片内寄存器中记录第一个错误的错误状态，以供以后分析。当士兵启动模式未启用并发生错误时，系统将停止处理，并将错误报告给操作系统。

7. 发明授权

US07584342B1 Parallel data processing systems and methods using cooperative thread arrays and SIMD instruction issue 有权
标题翻译：并行数据处理系统和方法使用协作线程数组和SIMD指令问题
公开(公告)号：US07584342B1
公开(公告)日：2009-09-01
申请号：US11305479
申请日：2005-12-15
申请人： Bryon S. Nordquist , John R. Nickolls , Luis I. Bacayo
发明人： Bryon S. Nordquist , John R. Nickolls , Luis I. Bacayo
IPC分类号： G06F15/80
CPC分类号： G06F9/52 , G06F9/3851 , G06F9/3887
摘要： Parallel data processing systems and methods use cooperative thread arrays (CTAs), i.e., groups of multiple threads that concurrently execute the same program on an input data set to produce an output data set. Each thread in a CTA has a unique identifier (thread ID) that can be assigned at thread launch time and that controls various aspects of the thread's processing behavior, such as the portion of the input data set to be processed by each thread, the portion of the output data set to be produced by each thread, and/or sharing of intermediate results among threads. Where groups of threads are executed in SIMD parallelism, thread IDs for threads in the same SIMD group are generated and assigned in parallel, allowing different SIMD groups to be launched in rapid succession.
摘要翻译：并行数据处理系统和方法使用协同线程数组（CIA），即在输入数据集上同时执行相同程序的多线程组，以产生输出数据集。 CTA中的每个线程都有一个唯一的标识符（线程ID），可以在线程启动时分配，并控制线程处理行为的各个方面，例如每个线程处理的输入数据集的部分，部分由每个线程产生的输出数据集合和/或线程之间的中间结果的共享。在SIMD并行执行线程组的情况下，并行生成并分配同一SIMD组中的线程的线程ID，从而允许快速连续启动不同的SIMD组。

8. 发明授权

US07522171B1 On-the-fly reordering of 32-bit per component texture images in a multi-cycle data transfer 有权
标题翻译：在多周期数据传输中，对32位每分量纹理图像进行即时重新排序
公开(公告)号：US07522171B1
公开(公告)日：2009-04-21
申请号：US11458952
申请日：2006-07-20
申请人： Bryon S. Nordquist
发明人： Bryon S. Nordquist
IPC分类号： G06F13/00 , G06F7/00 , G06F15/167 , G09G5/00 , G09G5/02 , G09G5/37
CPC分类号： G09G5/393 , G09G5/363 , G09G2360/18
摘要： A system of processing data in a graphics processing unit having a core configured to process data in hexadecimal form and other graphics modules configured to process data in quads includes a transpose buffer with a crossbar to reorganize incoming data, several memory banks to store the reorganized data over a period of several clock cycles, and a second crossbar for reorganizing the stored data after it is read from the bank of memories in one clock cycle. The method for converting between data in hexadecimal form and data in quads includes providing data in hexadecimal form, reorganizing the data provided in hexadecimal form, storing the reorganized data in several memories, and reading several of the memory locations, which contain all of the elements of the quad, in one clock cycle.
摘要翻译：在具有被配置为处理十六进制数据的核心的图形处理单元中处理数据的系统以及被配置为处理四边形数据的其它图形模块包括具有交叉开关以重组输入数据的转置缓冲器，若干存储体以存储重组数据在一个时钟周期的周期内，以及第二交叉开关，用于在从一个时钟周期的存储体读取之后重组所存储的数据。以十六进制形式的数据和四进制数据之间进行转换的方法包括以十六进制形式提供数据，重新组织以十六进制形式提供的数据，将重组数据存储在几个存储器中，以及读取几个存储单元，其中包含所有元素的四分之一，在一个时钟周期。

9. 发明授权

US07489315B1 Pixel stream assembly for raster operations 有权
标题翻译：用于光栅操作的像素流装配
公开(公告)号：US07489315B1
公开(公告)日：2009-02-10
申请号：US11421739
申请日：2006-06-01
申请人： Bryon S. Nordquist
发明人： Bryon S. Nordquist
IPC分类号： G09G5/36 , G09G5/00 , G09G5/02 , G06F13/00 , G06F17/00
CPC分类号： G09G5/363 , G09G5/02 , G09G5/22 , G09G5/393 , G09G2360/18
摘要： Systems and methods for converting graphics data represented in a hexadecimal form into a quad form may be used to reorganize the graphics data for performing raster operations. Prior to performing raster operations the graphics data received for each component is assembled to interleave the components for each pixel as needed to perform the raster operations. The assembly process varies depending on the number of bits per component, the number of components to be processed, and the memory format of the render target used to store the processed graphics data.
摘要翻译：用于将以十六进制形式表示的图形数据转换成四边形的系统和方法可用于重新组织用于执行光栅操作的图形数据。在执行光栅操作之前，为每个组件接收的图形数据被组合以根据需要对每个像素的组件进行交织以执行光栅操作。组装过程取决于每个组件的位数，要处理的组件的数量以及用于存储处理后的图形数据的渲染目标的存储器格式。

10. 发明授权

US07477260B1 On-the-fly reordering of multi-cycle data transfers 有权
标题翻译：多周期数据传输的即时重新排序
公开(公告)号：US07477260B1
公开(公告)日：2009-01-13
申请号：US11346478
申请日：2006-02-01
申请人： Bryon S. Nordquist
发明人： Bryon S. Nordquist
IPC分类号： G09G5/36 , G09G5/00 , G09G5/02 , G06F13/00 , G06F7/00
CPC分类号： G09G5/393 , G09G5/363 , G09G2360/18
摘要： A system of processing data in a graphics processing unit having a core configured to process data in hexadecimal form and other graphics modules configured to process data in quads includes a transpose buffer with a crossbar to reorganize incoming data, several memory banks to store the reorganized data over a period of several clock cycles, and a second crossbar for reorganizing the stored data after it is read from the bank of memories in one clock cycle. The method for converting between data in hexadecimal form and data in quads includes providing data in hexadecimal form, reorganizing the data provided in hexadecimal form, storing the reorganized data in several memories, and reading several of the memory locations, which contain all of the elements of the quad, in one clock cycle.
摘要翻译：在具有被配置为处理十六进制数据的核心的图形处理单元中处理数据的系统以及被配置为处理四边形数据的其它图形模块包括具有交叉开关以重组输入数据的转置缓冲器，若干存储体以存储重组数据在一个时钟周期的周期内，以及第二交叉开关，用于在从一个时钟周期的存储体读取之后重组所存储的数据。以十六进制形式的数据和四进制数据之间进行转换的方法包括以十六进制形式提供数据，重新组织以十六进制形式提供的数据，将重组数据存储在几个存储器中，以及读取几个存储单元，其中包含所有元素的四分之一，在一个时钟周期。

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