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1. 发明申请

US20120313679A1 PUMP CIRCUIT AND METHOD FOR PUMPING VOLTAGE IN SEMICONDUCTOR APPARATUS 审中-公开
标题翻译：泵电路及其在半导体装置中的电压抽运方法
公开(公告)号：US20120313679A1
公开(公告)日：2012-12-13
申请号：US13341004
申请日：2011-12-30
申请人： Chae Kyu JANG
发明人： Chae Kyu JANG
IPC分类号： H03L7/093
CPC分类号： H02M3/073 , H02M2003/076
摘要： A pump circuit includes a first clock generation unit, a second clock generation unit and a pumping stage unit. The first clock generation unit is configured to generate a first clock with a first amplitude by using an input clock and an external voltage. The second clock generation unit is configured to generate a second clock with a second amplitude larger than the first amplitude by using the input clock and an amplified voltage generated by amplifying the external voltage. The pumping stage unit is configured to increase an input voltage using the first clock and the second clock and generate amplified output voltages.
摘要翻译：泵电路包括第一时钟生成单元，第二时钟生成单元和泵送单元。第一时钟生成单元被配置为通过使用输入时钟和外部电压来产生具有第一幅度的第一时钟。第二时钟生成单元被配置为通过使用输入时钟和通过放大外部电压产生的放大电压来产生具有大于第一幅度的第二幅度的第二时钟。泵送级单元被配置为使用第一时钟和第二时钟增加输入电压并产生放大的输出电压。

2. 发明申请

US20120306470A1 DOWN-CONVERTING VOLTAGE GENERATING CIRCUIT 有权
标题翻译：下变频电压发生电路
公开(公告)号：US20120306470A1
公开(公告)日：2012-12-06
申请号：US13339034
申请日：2011-12-28
申请人： Chae Kyu JANG , Jong Hyun WANG , Sang Don LEE
发明人： Chae Kyu JANG , Jong Hyun WANG , Sang Don LEE
IPC分类号： G05F3/08
CPC分类号： G05F1/56
摘要： A down-converting voltage generating circuit includes a reference voltage providing unit, an initial setting unit, a driving unit, and a driving force control unit. The reference voltage providing unit provides a reference voltage to a first node. The initial setting unit drops a voltage level of the first node to substantially a level of a ground voltage when an initial setting signal is activated. The driving unit drives a down-converted voltage derived from an external voltage in response to the voltage level of the first node. The driving force control unit is connected to the driving unit, and controls a driving force for driving the down-converted voltage of the driving unit in response to the initial setting signal.
摘要翻译：下变频电压发生电路包括基准电压提供单元，初始设定单元，驱动单元和驱动力控制单元。参考电压提供单元向第一节点提供参考电压。当初始设置信号被激活时，初始设置单元将第一节点的电压电平降低到接地电压的大致水平。驱动单元驱动响应于第一节点的电压电平从外部电压导出的下变频电压。驱动力控制单元连接到驱动单元，并且响应于初始设置信号控制用于驱动驱动单元的下变频电压的驱动力。

3. 发明申请

US20120169396A1 VOLTAGE DOWN CONVERTER 有权
标题翻译：降压转换器
公开(公告)号：US20120169396A1
公开(公告)日：2012-07-05
申请号：US13331634
申请日：2011-12-20
申请人： Chae Kyu JANG
发明人： Chae Kyu JANG
IPC分类号： H03L5/00
CPC分类号： G11C5/147 , G05F1/575
摘要： A voltage down converter includes a first driver having a first input terminal configured to generate a first voltage by using an external voltage in response to a first driving signal being inputted to the first input terminal, a control circuit configured to output the first driving signal to the first input terminal in response to a level of the first voltage, a second driver having a second input terminal configured to generate a second voltage by using the external voltage in response to the first driving signal or a second driving signal being inputted to the second input terminal, wherein the first driving signal is transferred from the first input terminal to the second input terminal through a conductive line, and a driving control circuit configured to generate the second driving signal and transferred to the second input terminal in response to a level of the second voltage.
摘要翻译：降压转换器包括第一驱动器，第一驱动器具有第一输入端子，其被配置为响应于输入到第一输入端子的第一驱动信号通过使用外部电压产生第一电压;控制电路，被配置为将第一驱动信号输出到所述第一输入端子响应于所述第一电压的电平，第二驱动器具有第二输入端子，所述第二输入端子被配置为通过响应于所述第一驱动信号使用所述外部电压或者将第二驱动信号输入到所述第二驱动信号而产生第二电压输入端子，其中所述第一驱动信号通过导线从所述第一输入端子传送到所述第二输入端子;以及驱动控制电路，被配置为响应于所述第二驱动信号的电平而产生所述第二驱动信号并被传送到所述第二输入端子第二电压。

4. 发明授权

US08189388B2 Fuse circuit and flash memory device having the same 有权
标题翻译：保险丝电路和具有相同功能的闪存器件
公开(公告)号：US08189388B2
公开(公告)日：2012-05-29
申请号：US12839277
申请日：2010-07-19
申请人： Chae Kyu Jang
发明人： Chae Kyu Jang
IPC分类号： G11C11/34 , G11C16/06 , G11C17/00 , G11C17/18
CPC分类号： G11C17/16 , G11C17/18 , G11C29/785
摘要： A flash memory device includes a main cell array configured to have main memory cells for storing data and a redundancy cell array configured to have redundancy memory cells for repairing a failed memory cell of the main cell array. A page buffer circuit is configured to perform a program operation, a verifying operation and a read operation on the main cell array and the redundancy cell array. A repair circuit includes fuse circuits having fuse memory cells each of which is programmed in response to address information. The repair circuit is operated in response to a program state of the fuse memory cells and output a repair signal. A data input/output controller is configured to control input/output of data to/from the main memory cell or the redundancy memory cell in accordance with the repair signal outputted by the repair circuit.
摘要翻译：闪存器件包括：主单元阵列，被配置为具有用于存储数据的主存储单元;冗余单元阵列，被配置为具有用于修复主单元阵列的故障存储单元的冗余存储单元。页缓冲电路被配置为对主单元阵列和冗余单元阵列执行编程操作，验证操作和读操作。修复电路包括具有熔丝存储单元的熔丝电路，每个熔丝电路根据地址信息进行编程。修复电路响应于保险丝存储器单元的编程状态而被操作并输出修复信号。数据输入/输出控制器被配置为根据由修复电路输出的修复信号来控制到主存储器单元或冗余存储单元的数据输入/输出。

5. 发明申请

US20100284222A1 FUSE CIRCUIT AND FLASH MEMORY DEVICE HAVING THE SAME 有权
标题翻译：保险丝电路和具有该保险丝的闪存存储器件
公开(公告)号：US20100284222A1
公开(公告)日：2010-11-11
申请号：US12839277
申请日：2010-07-19
申请人： Chae Kyu Jang
发明人： Chae Kyu Jang
IPC分类号： G11C16/06 , G11C17/16
CPC分类号： G11C17/16 , G11C17/18 , G11C29/785
摘要： A flash memory device includes a main cell array configured to have main memory cells for storing data and a redundancy cell array configured to have redundancy memory cells for repairing a failed memory cell of the main cell array. A page buffer circuit is configured to perform a program operation, a verifying operation and a read operation on the main cell array and the redundancy cell array. A repair circuit includes fuse circuits having fuse memory cells each of which is programmed in response to address information. The repair circuit is operated in response to a program state of the fuse memory cells and output a repair signal. A data input/output controller is configured to control input/output of data to/from the main memory cell or the redundancy memory cell in accordance with the repair signal outputted by the repair circuit.
摘要翻译：闪存器件包括：主单元阵列，被配置为具有用于存储数据的主存储单元;冗余单元阵列，被配置为具有用于修复主单元阵列的故障存储单元的冗余存储单元。页缓冲电路被配置为对主单元阵列和冗余单元阵列执行编程操作，验证操作和读操作。修复电路包括具有熔丝存储单元的熔丝电路，每个熔丝电路根据地址信息进行编程。修复电路响应于保险丝存储器单元的编程状态而被操作并输出修复信号。数据输入/输出控制器被配置为根据由修复电路输出的修复信号来控制到主存储器单元或冗余存储单元的数据输入/输出。

6. 发明申请

US20100008137A1 NONVOLATILE MEMORY DEVICE AND PROGRAM OR ERASE METHOD USING THE SAME 失效
标题翻译：非易失性存储器件和使用其的程序或擦除方法
公开(公告)号：US20100008137A1
公开(公告)日：2010-01-14
申请号：US12493288
申请日：2009-06-29
申请人： Chae Kyu Jang , Seung Ho Chang , Young Soo Park , Jae Yun Kim , Se Chun Park
发明人： Chae Kyu Jang , Seung Ho Chang , Young Soo Park , Jae Yun Kim , Se Chun Park
IPC分类号： G11C16/06 , G11C16/04 , G11C7/06
CPC分类号： G11C16/10 , G11C16/14 , G11C16/28 , G11C16/30
摘要： A nonvolatile memory device includes a comparison unit configured to compare a reference voltage and a voltage of each of a plurality of nodes of a sample memory cell string, a state storage unit configured to store state information of each of memory cells depending on the corresponding comparison result of the comparison unit, and a high voltage generation unit configured to change a program start voltage depending on data stored in the state storage unit.
摘要翻译：非易失性存储器件包括：比较单元，被配置为比较采样存储单元串的多个节点的参考电压和电压;状态存储单元，被配置为根据相应的比较来存储每个存储器单元的状态信息比较单元的结果，以及被配置为根据存储在状态存储单元中的数据来改变程序开始电压的高电压生成单元。

7. 发明授权

US07499363B2 Semiconductor memory apparatus capable of reducing ground noise 有权
标题翻译：能够降低地面噪声的半导体存储装置
公开(公告)号：US07499363B2
公开(公告)日：2009-03-03
申请号：US11637080
申请日：2006-12-12
申请人： Dong Keun Kim , Chae Kyu Jang
发明人： Dong Keun Kim , Chae Kyu Jang
IPC分类号： G11C5/14 , G11C5/06 , G11C8/00
CPC分类号： G11C5/14 , G11C7/02
摘要： A semiconductor memory apparatus includes a bank that includes a core block where a memory cell array is disposed and a control block to drive the memory cell array, a ground power supply pad that is supplied with a ground power through a ground line, a switch that connects the ground line and the core block, and a block control unit that controls an on/off operation of the switch.
摘要翻译：一种半导体存储装置，具备包括配置有存储单元阵列的芯块和驱动存储单元阵列的控制块的存储体，通过地线提供接地电力的接地电源焊盘，连接地线和核心块，以及块控制单元，其控制开关的开/关操作。

8. 发明申请

US20090052247A1 FUSE CIRCUIT AND FLASH MEMORY DEVICE HAVING THE SAME 有权
标题翻译：保险丝电路和具有该保险丝的闪存存储器件
公开(公告)号：US20090052247A1
公开(公告)日：2009-02-26
申请号：US12016782
申请日：2008-01-18
申请人： Chae Kyu JANG
发明人： Chae Kyu JANG
IPC分类号： G11C29/00 , G11C17/18
CPC分类号： G11C17/16 , G11C17/18 , G11C29/785
摘要： A fuse circuit in a flash memory device is disclosed. The fuse circuit includes a plurality of memory cells turned on/off by a first voltage in accordance with program state, a switching circuit configured to switch in response to a control signal, thereby transmitting a verifying signal for verifying program of the memory cell to the memory cell, and a cell controller configured to output the verifying signal for controlling program, verification and erase of the memory cells and the control signal.
摘要翻译：公开了一种闪存器件中的熔丝电路。熔丝电路包括根据编程状态由第一电压导通/关断的多个存储器单元，切换电路被配置为响应于控制信号进行切换，从而将用于验证存储器单元的程序的验证信号发送到存储单元和单元控制器，其被配置为输出用于控制存储单元的控制程序，验证和擦除以及控制信号的验证信号。

9. 发明申请

US20080088362A1 CIRCUIT FOR SUPPLYING A VOLTAGE IN A MEMORY DEVICE 有权
标题翻译：用于在存储器件中提供电压的电路
公开(公告)号：US20080088362A1
公开(公告)日：2008-04-17
申请号：US11687459
申请日：2007-03-16
申请人： Chae Kyu JANG
发明人： Chae Kyu JANG
IPC分类号： G05F1/10
CPC分类号： G05F3/16
摘要： A circuit for supplying an operation voltage in a memory device includes a voltage supplying section that supplies a constant voltage to an output section through a first path and constantly discharges a portion of the supplied voltage through a second path. A third path section provides the supplied voltage to the output section through a third path in accordance with a controlling signal and a fourth path section discharges a portion of the voltage supplied from the voltage supplying section through a fourth path different from the second path in accordance with the controlling signal. A controller is configured to output the controlling signal that controlling the third and fourth path sections in accordance with an operation mode in the memory device. The circuit controls a dead zone window in accordance with a mode, thereby preventing an unnecessary consumption of power.
摘要翻译：用于在存储器件中提供操作电压的电路包括：电压提供部分，通过第一路径向输出部分提供恒定电压，并通过第二路径恒定地排出所提供的电压的一部分。第三路径部分根据控制信号通过第三路径向输出部分提供所提供的电压，并且第四路径部分按照与第二路径不同的第四路径从电压供应部分提供的电压的一部分放电与控制信号。控制器被配置为根据存储装置中的操作模式输出控制第三和第四路径部分的控制信号。电路根据模式控制死区窗，从而防止不必要的电力消耗。

10. 发明授权

US07276941B2 Power up circuit of semiconductor memory device and compensating method thereof 有权
标题翻译：半导体存储器件的上电电路及其补偿方法
公开(公告)号：US07276941B2
公开(公告)日：2007-10-02
申请号：US11020309
申请日：2004-12-27
申请人： Chae-Kyu Jang
发明人： Chae-Kyu Jang
IPC分类号： H03L7/00
CPC分类号： H03K17/223
摘要： There is provided a power up circuit capable of outputting a power up signal delayed by a predetermined time. The power up circuit includes a voltage divider for dividing an external voltage, a delay controller for generating a control signal to control an output voltage of the voltage divider for a predetermined time by using the external voltage, and a signal generator for generating a power up signal delayed by a predetermined time by using the control signal.
摘要翻译：提供了能够输出延迟预定时间的上电信号的上电电路。上电电路包括用于分割外部电压的分压器，用于产生控制信号以通过使用外部电压来控制分压器的输出电压达预定时间的延迟控制器，以及用于产生上电的信号发生器信号通过使用控制信号延迟预定时间。

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