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1. 发明授权

US08605722B1 Deadlock-resistant fabric tree replication in a network device 有权
公开(公告)号：US08605722B1
公开(公告)日：2013-12-10
申请号：US12759850
申请日：2010-04-14
申请人： Pradeep Sindhu , Jean-Marc Frailong , Sarin Thomas , Srihari Vegesna , David J. Ofelt , Chang-Hong Wu
发明人： Pradeep Sindhu , Jean-Marc Frailong , Sarin Thomas , Srihari Vegesna , David J. Ofelt , Chang-Hong Wu
IPC分类号： H04L12/28
CPC分类号： H04L45/16 , H04L12/1863 , H04L49/201 , H04L49/90 , H04L67/1095
摘要： In general, the invention is directed to techniques for reducing deadlocks that may arise when performing fabric replication. For example, as described herein, a network device includes packet replicators that each comprises a plurality of resource partitions. A replication data structure for a packet received by the network device includes packet replicator nodes that are arranged hierarchically to occupy one or more levels of the replication data structure. Each of the resource partitions in each of the plurality of packet replicators is associated with a different level of the replication data structure. The packet replicators replicate the packet according to the replication data structure, and each of the packet replicators handles the packet using the one of the resource partitions of the packet replicator that is associated with the level of the replication data structure occupied by the node that corresponds to that particular packet replicator.

2. 发明授权

US08452908B2 Low latency serial memory interface 有权
标题翻译：低延迟串行存储器接口
公开(公告)号：US08452908B2
公开(公告)日：2013-05-28
申请号：US12648373
申请日：2009-12-29
申请人： David P. Chengson , Chang-Hong Wu
发明人： David P. Chengson , Chang-Hong Wu
IPC分类号： G06F13/14 , G06F3/00 , G06F5/00 , G06F1/04 , G06F1/12 , G06F5/06
CPC分类号： G06F13/1689 , H04L25/03866 , H04L25/06
摘要： A device applies synchronous clocking across a first component and a second component of the device, and designates a particular serial link, from a group of serial links, as a master serial link. The device also designates the remaining serial links as slave serial links, provides, via the master serial link, an encoded data stream, and provides, via the slave serial links, un-encoded and scrambled data streams.
摘要翻译：一个设备跨设备的第一个组件和第二个组件应用同步时钟，并从一组串行链路指定一个特定的串行链路作为主串行链路。该设备还将剩余的串行链路指定为从串行链路，通过主串行链路提供编码数据流，并通过从串行链路提供未编码和加扰的数据流。

3. 发明授权

US06675307B1 Clock controller for controlling the switching to redundant clock signal without producing glitches by delaying the redundant clock signal to match a phase of primary clock signal 有权
标题翻译：时钟控制器，用于通过延迟冗余时钟信号来匹配主时钟信号的相位来控制切换到冗余时钟信号而不产生毛刺
公开(公告)号：US06675307B1
公开(公告)日：2004-01-06
申请号：US09536886
申请日：2000-03-28
申请人： Ross S. Heitkamp , Chang-Hong Wu
发明人： Ross S. Heitkamp , Chang-Hong Wu
IPC分类号： G06F112
CPC分类号： G06F1/12
摘要： A system and method for controlling clocking signals including a clock controller that includes a first input operable to receive a first clock signal having a first frequency, a second input operable to receive a second clock having a same frequency as the first clock signal but of arbitrary phase, a first output and a variable delay line coupling the first clock signal received at the first input to the first output. The first output is operable to couple a delayed version of the first clock signal to the receiving device. The clock controller includes a comparator receiving as an input the first and the second clock signals from the first and second inputs and providing as an output to the variable delay line a control signal for adjusting a delay in the first clock signal so as to match a phase of the second clock signal received at the receiving device.
摘要翻译：一种用于控制时钟信号的系统和方法，包括时钟控制器，时钟控制器包括可操作以接收具有第一频率的第一时钟信号的第一输入端，可操作以接收具有与第一时钟信号相同频率但任意的第二时钟的第二时钟的第二输入相位，第一输出和可变延迟线，将在第一输入处接收的第一时钟信号耦合到第一输出。第一输出可操作以将第一时钟信号的延迟版本耦合到接收装置。时钟控制器包括一个比较器，用于从第一和第二输入端接收第一和第二时钟信号作为输入，并向可变延迟线提供用于调整第一时钟信号延迟的控制信号，以便匹配一个在接收设备处接收的第二时钟信号的相位。

4. 发明授权

US08520522B1 Transmit-buffer management for priority-based flow control 有权
标题翻译：发送缓冲区管理，用于基于优先级的流量控制
公开(公告)号：US08520522B1
公开(公告)日：2013-08-27
申请号：US12905696
申请日：2010-10-15
申请人： Gary Goldman , Paul Kim , Chang-Hong Wu
发明人： Gary Goldman , Paul Kim , Chang-Hong Wu
IPC分类号： H04L12/26
CPC分类号： H04L47/26 , H04L47/29 , H04L47/30
摘要： A network device operating in operating in a Priority Flow Control (PFC) mode receives a stream of packets for outputting on a particular port, assigns each packet in the stream of packets to one of multiple buffer queues associated with the port, and generates, based on the assigning, packet counts for the multiple buffer queues. The network device aggregates the packet counts for a group of particular buffer queues, of the multiple buffer queues, that are not subject to a PFC restriction, to create an unrestricted aggregated count. The network device determines whether the unrestricted aggregated count exceeds a flow-control threshold for the group of particular buffer queues and sends, to an upstream queue scheduler, a flow control signal when the unrestricted aggregated count exceeds a flow-control threshold.
摘要翻译：以优先级流量控制（PFC）模式操作的网络设备接收用于在特定端口上输出的分组流，将分组流中的每个分组分配给与端口相关联的多个缓冲器队列之一，并基于对多个缓冲区队列的分配计数。网络设备聚合不受PFC限制的多个缓冲区队列的一组特定缓冲队列的分组计数，以创建无限制的聚合计数。网络设备确定无限制聚合计数是否超过特定缓冲队列组的流量控制阈值，并且当无限制聚合计数超过流量控制阈值时，向上游队列调度器发送流控制信号。

5. 发明申请

US20110235642A1 PRESERVING THE ORDER OF PACKETS THROUGH A DEVICE 审中-公开
标题翻译：通过设备保存包装的订单
公开(公告)号：US20110235642A1
公开(公告)日：2011-09-29
申请号：US13153799
申请日：2011-06-06
申请人： Stefan DYCKERHOFF , Pankaj Patel , Pradeep Sindhu , Ashok Krishnamurthi , Hann-Hwan Ju , Ramalingam K. Anand , Dennis C. Ferguson , Chang-Hong Wu
发明人： Stefan DYCKERHOFF , Pankaj Patel , Pradeep Sindhu , Ashok Krishnamurthi , Hann-Hwan Ju , Ramalingam K. Anand , Dennis C. Ferguson , Chang-Hong Wu
IPC分类号： H04L12/56
CPC分类号： H04L45/00 , H04L45/60 , H04L47/125 , H04L49/103 , H04L49/45 , H04L49/552
摘要： A network device includes one or more sprayers, multiple packet processors, and one or more desprayers. The sprayers receive packets on at least one incoming packet stream and distribute the packets according to a load balancing scheme that balances the number of bytes of packet data that is given to each of the packet processors. The packet processors receive the packets from the sprayers and process the packets to determine routing information for the packets. The desprayers receive the processed packets from the packet processors and transmit the packets on at least one outgoing packet stream based on the routing information.
摘要翻译：网络设备包括一个或多个喷雾器，多个分组处理器和一个或多个解卷器。喷雾器在至少一个输入分组流上接收分组，并根据负载平衡方案分发分组，该负载平衡方案平衡给予每个分组处理器的分组数据的字节数。分组处理器接收来自喷雾器的分组，并处理分组以确定分组的路由信息。解散器从分组处理器接收处理的分组，并基于路由信息在至少一个输出分组流上传送分组。

6. 发明申请

US20100158031A1 METHODS AND APPARATUS FOR TRANSMISSION OF GROUPS OF CELLS VIA A SWITCH FABRIC 有权
标题翻译：用于通过开关织物传输细胞群的方法和装置
公开(公告)号：US20100158031A1
公开(公告)日：2010-06-24
申请号：US12343728
申请日：2008-12-24
申请人： Sarin Thomas , Srihari Vegesna , Pradeep Sindhu , Chi-Chung Kenny Chen , Jean-Marc Frailong , David J. Ofelt , Philip A. Thomas , Chang-Hong Wu
发明人： Sarin Thomas , Srihari Vegesna , Pradeep Sindhu , Chi-Chung Kenny Chen , Jean-Marc Frailong , David J. Ofelt , Philip A. Thomas , Chang-Hong Wu
IPC分类号： H04L12/56
CPC分类号： H04J3/00 , H04L49/251 , H04L49/254
摘要： In one embodiment, a method can include receiving at an egress schedule module a request to schedule transmission of a group of cells from an ingress queue through a switch fabric of a multi-stage switch. The ingress queue can be associated with an ingress stage of the multi-stage switch. The egress schedule module can be associated with an egress stage of the multi-stage switch. The method can also include determining, in response to the request, that an egress port at the egress stage of the multi-stage switch is available to transmit the group of cells from the multi-stage switch.
摘要翻译：在一个实施例中，一种方法可以包括在出口调度模块处接收通过多级交换机的交换结构调度来自进入队列的小区的传输的请求。入站队列可以与多级交换机的进入级相关联。出口调度模块可以与多级交换机的出口级相关联。该方法还可以包括响应于该请求确定多级交换机的出口级的出口端口可用于从多级交换机发送小区组。

7. 发明授权

US06810501B1 Single cycle cyclic redundancy checker/generator 有权
标题翻译：单周期循环冗余校验器/发生器
公开(公告)号：US06810501B1
公开(公告)日：2004-10-26
申请号：US09752829
申请日：2001-01-03
申请人： Dennis C. Ferguson , Devereaux C. Chen , Ramesh Padmanabhan , Chang-Hong Wu , Thomas Michael Skibo
发明人： Dennis C. Ferguson , Devereaux C. Chen , Ramesh Padmanabhan , Chang-Hong Wu , Thomas Michael Skibo
IPC分类号： H03M1300
CPC分类号： H03M13/091
摘要： A system updates a cyclic redundancy check (CRC) value. The system receives data containing an arbitrary number of valid and invalid portions. The valid portions are positioned adjacent to one another. The system also receives a signal representing a quantity of valid portions in the data and a current CRC value. The system updates the current CRC value using the data and signal in a single clock cycle.
摘要翻译：系统更新循环冗余校验（CRC）值。系统接收包含任意数量的有效和无效部分的数据。有效部分彼此相邻地定位。该系统还接收表示数据中有效部分的数量的信号和当前的CRC值。系统在单个时钟周期内使用数据和信号更新当前CRC值。

8. 发明授权

US06429706B1 Voltage sequencing circuit for powering-up sensitive electrical components 有权
标题翻译：用于上电敏感电气元件的电压排序电路
公开(公告)号：US06429706B1
公开(公告)日：2002-08-06
申请号：US09983423
申请日：2001-10-24
申请人： Dilip A. Amin , Chang Hong Wu , Ross Heitkamp , Michael Armstrong
发明人： Dilip A. Amin , Chang Hong Wu , Ross Heitkamp , Michael Armstrong
IPC分类号： H03L700
CPC分类号： G06F1/26
摘要： A voltage sequencing circuit powers-up electrical systems by sequentially enabling a series of power supply lines to the electrical system. After each power supply line is enabled, the voltage sequencing circuit waits a pre-programmed delay time before enabling the next power supply line. The delay time allows the newly enabled power supply line to settle. Additionally, the voltage sequencing circuit constantly monitors previously enabled power supply lines while continuing to enable the remaining power supply lines. If any of the previously enabled lines fail, the voltage sequencing circuit disables the power supply line before reinitiating a complete power-up sequence.
摘要翻译：电压排序电路通过依次启用电气系统的一系列电源线来加电电气系统。在每个电源线被使能之后，电压排序电路在启用下一个电源线之前等待预编程的延迟时间。延迟时间允许新启用的电源线路稳定。此外，电压排序电路持续监视先前启用的电源线，同时继续启用剩余的电源线。如果任何先前启用的线路故障，则电压排序电路在重新启动完整的上电序列之前禁用电源线。

9. 发明授权

US06333650B1 Voltage sequencing circuit for powering-up sensitive electrical components 有权
标题翻译：用于上电敏感电气元件的电压排序电路
公开(公告)号：US06333650B1
公开(公告)日：2001-12-25
申请号：US09729239
申请日：2000-12-05
申请人： Dilip A. Amin , Chang Hong Wu , Ross Heitkamp , Michael Armstrong
发明人： Dilip A. Amin , Chang Hong Wu , Ross Heitkamp , Michael Armstrong
IPC分类号： H03L700
CPC分类号： G06F1/26
摘要： A voltage sequencing circuit powers-up electrical systems by sequentially enabling a series of power supply lines to the electrical system. After each power supply line is enabled, the voltage sequencing circuit waits a pre-programmed delay time before enabling the next power supply line. The delay time allows the newly enabled power supply line to settle. Additionally, the voltage sequencing circuit constantly monitors previously enabled power supply lines while continuing to enable the remaining power supply lines. If any of the previously enabled lines fail, the voltage sequencing circuit disables the power supply line before reinitiating a complete power-up sequence.
摘要翻译：电压排序电路通过依次启用电气系统的一系列电源线来加电电气系统。在每个电源线被使能之后，电压排序电路在启用下一个电源线之前等待预编程的延迟时间。延迟时间允许新启用的电源线路稳定。此外，电压排序电路持续监视先前启用的电源线，同时继续启用剩余的电源线。如果任何先前启用的线路故障，则电压排序电路在重新启动完整的上电序列之前禁用电源线。

10. 发明授权

US08325749B2 Methods and apparatus for transmission of groups of cells via a switch fabric 有权
标题翻译：用于经由交换结构传输小区组的方法和装置
公开(公告)号：US08325749B2
公开(公告)日：2012-12-04
申请号：US12343728
申请日：2008-12-24
申请人： Sarin Thomas , Srihari Vegesna , Pradeep Sindhu , Chi-Chung Kenny Chen , Jean-Marc Frailong , David J. Ofelt , Philip A. Thomas , Chang-Hong Wu
发明人： Sarin Thomas , Srihari Vegesna , Pradeep Sindhu , Chi-Chung Kenny Chen , Jean-Marc Frailong , David J. Ofelt , Philip A. Thomas , Chang-Hong Wu
IPC分类号： H04L12/28
CPC分类号： H04J3/00 , H04L49/251 , H04L49/254
摘要： In one embodiment, a method can include receiving at an egress schedule module a request to schedule transmission of a group of cells from an ingress queue through a switch fabric of a multi-stage switch. The ingress queue can be associated with an ingress stage of the multi-stage switch. The egress schedule module can be associated with an egress stage of the multi-stage switch. The method can also include determining, in response to the request, that an egress port at the egress stage of the multi-stage switch is available to transmit the group of cells from the multi-stage switch.
摘要翻译：在一个实施例中，一种方法可以包括在出口调度模块处接收通过多级交换机的交换结构调度来自进入队列的小区的传输的请求。入站队列可以与多级交换机的进入级相关联。出口调度模块可以与多级交换机的出口级相关联。该方法还可以包括响应于该请求确定多级交换机的出口级的出口端口可用于从多级交换机发送小区组。

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