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1. 发明授权

US07000097B2 System and method for handling load and/or store operations in a superscalar microprocessor 失效
公开(公告)号：US07000097B2
公开(公告)日：2006-02-14
申请号：US10185007
申请日：2002-07-01
申请人： Cheryl D. Senter , Johannes Wang
发明人： Cheryl D. Senter , Johannes Wang
IPC分类号： G06F9/34 , G06F9/44 , G06F9/312
CPC分类号： G06F9/3826 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/3834 , G06F9/3853
摘要： The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load store unit are: (1) handling out of order cache requests; (2) detecting address collisions; and (3) alignment of data.

2. 发明授权

US06957320B2 System and method for handling load and/or store operations in a superscalar microprocessor 失效
标题翻译：用于在超标量微处理器中处理负载和/或存储操作的系统和方法
公开(公告)号：US06957320B2
公开(公告)日：2005-10-18
申请号：US10190703
申请日：2002-07-09
申请人： Cheryl D. Senter , Johannes Wang
发明人： Cheryl D. Senter , Johannes Wang
IPC分类号： G06F9/00 , G06F9/312 , G06F9/318 , G06F9/38 , G06F12/04
CPC分类号： G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3017 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load store unit are: (1) handling out of order cache requests; (2) detecting address collisions; and (3) alignment of data.
摘要翻译：本发明提供一种用于管理在超标量RISC架构环境中读取和写入存储器或I / O所需的负载和存储操作的系统和方法。为了执行此任务，提供了一个加载存储单元，其主要目的是尽可能地使加载请求失效，以便尽可能快地将加载数据返回供指令执行单元使用。如果没有地址冲突而没有写入，只能执行加载操作。当在较旧的指令写入的存储器位置请求读取时，发生地址冲突。写入挂起是指较旧的指令请求存储操作，但存储地址尚未计算的情况。数据高速缓存单元返回8字节的未对齐数据。加载/存储单元在返回指令执行单元之前将其正确对齐。因此，加载存储单元的三个主要任务是：（1）处理无序缓存请求; （2）检测地址冲突; 和（3）数据对齐。

3. 发明授权

US06735685B1 System and method for handling load and/or store operations in a superscalar microprocessor 失效
标题翻译：用于在超标量微处理器中处理负载和/或存储操作的系统和方法
公开(公告)号：US06735685B1
公开(公告)日：2004-05-11
申请号：US09336589
申请日：1999-06-21
申请人： Cheryl D. Senter , Johannes Wang
发明人： Cheryl D. Senter , Johannes Wang
IPC分类号： G06F930
CPC分类号： G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3017 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load/store unit is provided whose main purpose is to make load requests out-of-order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out-of-order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load/store unit are: (1) handling out of order cache requests; (2) detecting address collisions; and (3) alignment of data.
摘要翻译：本发明提供一种用于管理在超标量RISC架构环境中读取和写入存储器或I / O所需的负载和存储操作的系统和方法。为了执行此任务，提供了一个加载/存储单元，其主要目的是使可能的负载请求无序地尽可能快地获得负载数据以供指令执行单元使用。如果没有地址冲突，没有写入，只能执行加载操作。当在较旧的指令写入的存储器位置请求读取时，发生地址冲突。写入挂起是指较旧的指令请求存储操作，但存储地址尚未计算的情况。数据高速缓存单元返回8字节的未对齐数据。加载/存储单元在返回指令执行单元之前将其正确对齐。因此，加载/存储单元的三个主要任务是：（1）处理无序缓存请求; （2）检测地址冲突; 和（3）数据对齐。

4. 发明申请

US20090217001A1 System and Method for Handling Load and/or Store Operations in a Superscalar Microprocessor 失效
标题翻译：在超标量微处理器中处理加载和/或存储操作的系统和方法
公开(公告)号：US20090217001A1
公开(公告)日：2009-08-27
申请号：US12436607
申请日：2009-05-06
申请人： Cheryl D. Senter , Johannes Wang
发明人： Cheryl D. Senter , Johannes Wang
IPC分类号： G06F9/30 , G06F9/312 , G06F12/02
CPC分类号： G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3017 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load store unit are: (1) handling out of order cache requests; (2) detecting address collisions; and (3) alignment of data.
摘要翻译：本发明提供一种用于管理在超标量RISC架构环境中读取和写入存储器或I / O所需的负载和存储操作的系统和方法。为了执行此任务，提供了一个加载存储单元，其主要目的是尽可能地使加载请求失效，以便尽可能快地将加载数据返回供指令执行单元使用。如果没有地址冲突而没有写入，只能执行加载操作。当在较旧的指令写入的存储器位置请求读取时，发生地址冲突。写入挂起是指较旧的指令请求存储操作，但存储地址尚未计算的情况。数据高速缓存单元返回8字节的未对齐数据。加载/存储单元在返回到指令执行单元之前将其正确对齐。因此，加载存储单元的三个主要任务是：（1）处理无序缓存请求; （2）检测地址冲突; 和（3）数据对齐。

5. 发明授权

US07447876B2 System and method for handling load and/or store operations in a superscalar microprocessor 失效
标题翻译：用于在超标量微处理器中处理负载和/或存储操作的系统和方法
公开(公告)号：US07447876B2
公开(公告)日：2008-11-04
申请号：US11107824
申请日：2005-04-18
申请人： Cheryl D. Senter , Johannes Wang
发明人： Cheryl D. Senter , Johannes Wang
IPC分类号： G06F9/30 , G06F9/312 , G06F9/26
CPC分类号： G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3017 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load store unit are: (1) handling out of order cache requests; (2) detecting address collisions; and (3) alignment of data.
摘要翻译：本发明提供一种用于管理在超标量RISC架构环境中读取和写入存储器或I / O所需的负载和存储操作的系统和方法。为了执行此任务，提供了一个加载存储单元，其主要目的是尽可能地使加载请求失效，以便尽可能快地将加载数据返回供指令执行单元使用。如果没有地址冲突而没有写入，只能执行加载操作。当在较旧的指令写入的存储器位置请求读取时，发生地址冲突。写入挂起是指较旧的指令请求存储操作，但存储地址尚未计算的情况。数据高速缓存单元返回8字节的未对齐数据。加载/存储单元在返回指令执行单元之前将其正确对齐。因此，加载存储单元的三个主要任务是：（1）处理无序缓存请求; （2）检测地址冲突; 和（3）数据对齐。

6. 发明授权

US5659782A System and method for handling load and/or store operations in a superscalar microprocessor 失效
标题翻译：用于在超标量微处理器中处理负载和/或存储操作的系统和方法
公开(公告)号：US5659782A
公开(公告)日：1997-08-19
申请号：US307042
申请日：1994-09-16
申请人： Cheryl D. Senter , Johannes Wang
发明人： Cheryl D. Senter , Johannes Wang
IPC分类号： G06F12/08 , G06F9/30 , G06F9/312 , G06F9/318 , G06F9/34 , G06F9/38 , G06F12/00 , G06F9/40
CPC分类号： G06F9/3826 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/3834 , G06F9/3853
摘要： The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load store unit are: (1) handling out of order cache requests; (2) detecting address collisions; and (3) alignment of data;
摘要翻译：本发明提供一种用于管理在超标量RISC架构环境中读取和写入存储器或I / O所需的负载和存储操作的系统和方法。为了执行此任务，提供了一个加载存储单元，其主要目的是尽可能地使加载请求失效，以便尽可能快地将加载数据返回供指令执行单元使用。如果没有地址冲突而没有写入，只能执行加载操作。当在较旧的指令写入的存储器位置请求读取时，发生地址冲突。写入挂起是指较旧的指令请求存储操作，但存储地址尚未计算的情况。数据高速缓存单元返回8字节的未对齐数据。加载/存储单元在返回指令执行单元之前将其正确对齐。因此，加载存储单元的三个主要任务是：（1）处理无序缓存请求; （2）检测地址冲突; 和（3）数据对齐;

7. 发明授权

US5557763A System for handling load and/or store operations in a superscalar microprocessor 失效
标题翻译：用于在超标量微处理器中处理负载和/或存储操作的系统
公开(公告)号：US5557763A
公开(公告)日：1996-09-17
申请号：US465238
申请日：1995-06-05
申请人： Cheryl D. Senter , Johannes Wang
发明人： Cheryl D. Senter , Johannes Wang
IPC分类号： G06F12/08 , G06F9/30 , G06F9/312 , G06F9/318 , G06F9/34 , G06F9/38 , G06F12/00
CPC分类号： G06F9/3826 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/3834 , G06F9/3853
摘要： The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load store unit are: (1) handling out of order cache requests; (2) detecting address collision; and (3) alignment of data.
摘要翻译：本发明提供一种用于管理在超标量RISC架构环境中读取和写入存储器或I / O所需的负载和存储操作的系统和方法。为了执行此任务，提供了一个加载存储单元，其主要目的是尽可能地使加载请求失效，以便尽可能快地将加载数据返回供指令执行单元使用。如果没有地址冲突而没有写入，只能执行加载操作。当在较旧的指令写入的存储器位置请求读取时，发生地址冲突。写入挂起是指较旧的指令请求存储操作，但存储地址尚未计算的情况。数据高速缓存单元返回8字节的未对齐数据。加载/存储单元在返回指令执行单元之前将其正确对齐。因此，加载存储单元的三个主要任务是：（1）处理无序缓存请求; （2）检测地址冲突; 和（3）数据对齐。

8. 发明授权

US07844797B2 System and method for handling load and/or store operations in a superscalar microprocessor 失效
标题翻译：用于在超标量微处理器中处理负载和/或存储操作的系统和方法
公开(公告)号：US07844797B2
公开(公告)日：2010-11-30
申请号：US12436607
申请日：2009-05-06
申请人： Cheryl D. Senter , Johannes Wang
发明人： Cheryl D. Senter , Johannes Wang
IPC分类号： G06F15/00
CPC分类号： G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3017 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load store unit are: (1) handling out of order cache requests; (2) detecting address collisions; and (3) alignment of data.
摘要翻译：本发明提供一种用于管理在超标量RISC架构环境中读取和写入存储器或I / O所需的负载和存储操作的系统和方法。为了执行此任务，提供了一个加载存储单元，其主要目的是尽可能地使加载请求失效，以便尽可能快地将加载数据返回供指令执行单元使用。如果没有地址冲突而没有写入，只能执行加载操作。当在较旧的指令写入的存储器位置请求读取时，发生地址冲突。写入挂起是指较旧的指令请求存储操作，但存储地址尚未计算的情况。数据高速缓存单元返回8字节的未对齐数据。加载/存储单元在返回指令执行单元之前将其正确对齐。因此，加载存储单元的三个主要任务是：（1）处理无序缓存请求; （2）检测地址冲突; 和（3）数据对齐。

9. 发明授权

US07861069B2 System and method for handling load and/or store operations in a superscalar microprocessor 失效
公开(公告)号：US07861069B2
公开(公告)日：2010-12-28
申请号：US11640968
申请日：2006-12-19
申请人： Cheryl D. Senter , Johannes Wang
发明人： Cheryl D. Senter , Johannes Wang
IPC分类号： G06F9/00
CPC分类号： G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3017 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857 , G06F9/3885
摘要： The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load store unit are: (1) handling out of order cache requests; (2) detecting address collisions; and (3) alignment of data.

10. 发明授权

US06434693B1 System and method for handling load and/or store operations in a superscalar microprocessor 失效
标题翻译：用于在超标量微处理器中处理负载和/或存储操作的系统和方法
公开(公告)号：US06434693B1
公开(公告)日：2002-08-13
申请号：US09438359
申请日：1999-11-12
申请人： Cheryl D. Senter , Johannes Wang
发明人： Cheryl D. Senter , Johannes Wang
IPC分类号： G06F9312
CPC分类号： G06F9/3826 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/30167 , G06F9/3816 , G06F9/3824 , G06F9/3834 , G06F9/3853
摘要： The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address-collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit. Thus, the three main tasks of the load store unit are: (1) handling out of order cache requests; (2) detecting address collision; and (3) alignment of data.
摘要翻译：本发明提供一种用于管理在超标量RISC架构环境中读取和写入存储器或I / O所需的负载和存储操作的系统和方法。为了执行此任务，提供了一个加载存储单元，其主要目的是尽可能地使加载请求失效，以便尽可能快地将加载数据返回供指令执行单元使用。如果没有地址冲突并且没有写入挂起，加载操作只能按顺序执行。当在较旧的指令写入的存储器位置请求读取时，发生地址冲突。写入挂起是指较旧的指令请求存储操作，但存储地址尚未计算的情况。数据高速缓存单元返回8字节的未对齐数据。加载/存储单元在返回到指令执行单元之前将其正确对齐。因此，加载存储单元的三个主要任务是：（1）处理无序缓存请求; （2）检测地址冲突; 和（3）数据对齐。

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