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1. 发明申请

US20100211837A1 Semiconductor test system with self-inspection of memory repair analysis 有权
标题翻译：半导体测试系统具有自检内存修复分析
公开(公告)号：US20100211837A1
公开(公告)日：2010-08-19
申请号：US12585016
申请日：2009-09-01
申请人： Chia-Ching Peng
发明人： Chia-Ching Peng
IPC分类号： G11C29/08 , G06F11/26
CPC分类号： G11C29/44 , G11C29/02 , G11C29/4401
摘要： A semiconductor test system with self-inspection of memory repair analysis is disclosed, comprising a memory repair analysis device, an analysis fail memory and a self-inspection controller. The self-inspection controller controls storing a set of simulated fail bit addresses and a set of simulated repair line addresses, provided from outside, into the analysis fail memory in advance, controls the memory repair analysis device to execute a particular repair analysis operation with respect to the set of simulated fail bit addresses to produce repair line address information, and compares the repair line address information, obtained after calculation, directly with the set of simulated repair line addresses in the analysis fail memory. Thus, before physically proceeding with the operation of testing, the invention is capable of self-inspecting if there is an abnormal condition of the memory repair analysis device and the analysis fail memory contained therein.
摘要翻译：公开了一种具有记忆修复分析自检的半导体测试系统，包括存储器修复分析设备，分析失败存储器和自检控制器。自检控制器控制存储从外部提供的一组模拟故障位地址和一组模拟修复线地址到预先分析故障存储器中，控制存储器修复分析设备执行特定的修复分析操作到一组模拟故障位地址以产生修理线地址信息，并将计算后获得的修复线地址信息与分析失败存储器中的一组模拟维修线地址直接进行比较。因此，在物理进行测试操作之前，如果存储器修复分析装置的异常状况和其中包含的分析失败存储器，本发明能够进行自检。

2. 发明授权

US07890820B2 Semiconductor test system with self-inspection of memory repair analysis 有权
标题翻译：半导体测试系统具有自检内存修复分析
公开(公告)号：US07890820B2
公开(公告)日：2011-02-15
申请号：US12585016
申请日：2009-09-01
申请人： Chia-Ching Peng
发明人： Chia-Ching Peng
IPC分类号： G11C29/00
CPC分类号： G11C29/44 , G11C29/02 , G11C29/4401
摘要： A semiconductor test system with self-inspection of memory repair analysis is disclosed, comprising a memory repair analysis device, an analysis fail memory and a self-inspection controller. The self-inspection controller controls storing a set of simulated fail bit addresses and a set of simulated repair line addresses, provided from outside, into the analysis fail memory in advance, controls the memory repair analysis device to execute a particular repair analysis operation with respect to the set of simulated fail bit addresses to produce repair line address information, and compares the repair line address information, obtained after calculation, directly with the set of simulated repair line addresses in the analysis fail memory. Thus, before physically proceeding with the operation of testing, the invention is capable of self-inspecting if there is an abnormal condition of the memory repair analysis device and the analysis fail memory contained therein.
摘要翻译：公开了一种具有记忆修复分析自检的半导体测试系统，包括存储器修复分析设备，分析失败存储器和自检控制器。自检控制器控制存储从外部提供的一组模拟故障位地址和一组模拟修复线地址到预先分析故障存储器中，控制存储器修复分析设备执行特定的修复分析操作到一组模拟故障位地址以产生修理线地址信息，并将计算后获得的修复线地址信息与分析失败存储器中的一组模拟维修线地址直接进行比较。因此，在物理进行测试操作之前，如果存储器修复分析装置的异常状况和其中包含的分析失败存储器，本发明能够进行自检。

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