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1. 发明申请

US20120133374A1 METHOD FOR DETECTING CAPACITOR LOSS 审中-公开
标题翻译：检测电容器损耗的方法
公开(公告)号：US20120133374A1
公开(公告)日：2012-05-31
申请号：US13070194
申请日：2011-03-23
申请人： Chih-Jen Chin , Quan-Jie Zheng , Ping Song , Chih-Feng Chen
发明人： Chih-Jen Chin , Quan-Jie Zheng , Ping Song , Chih-Feng Chen
IPC分类号： G01R31/12
CPC分类号： G01R31/028
摘要： A method for detecting a capacitor loss is applicable to detecting a plurality of by-pass capacitors connected in parallel to each other. The detection method includes the following steps, an alternating current (AC) signal is input into the by-pass capacitors, in which the AC signal has a plurality of test frequencies; test voltages of the by-pass capacitors at each of the test frequencies are recorded, so as to form a test result table; it is determined whether the test result table is the same as a standard voltage table; and when a result of the determination is NO, a fail signal is output. By applying the detection method, whether a loss exists in the by-pass capacitors can be effectively identified, thereby solving the problem that small capacitors are undetectable when large capacitors are connected in parallel to the small capacitors.
摘要翻译：用于检测电容器损耗的方法适用于检测彼此并联连接的多个旁路电容器。检测方法包括以下步骤：将交流信号输入到旁路电容器，其中交流信号具有多个测试频率; 记录各测试频率处旁路电容器的测试电压，形成测试结果表; 确定测试结果表是否与标准电压表相同; 并且当确定的结果为否时，输出故障信号。通过应用检测方法，可以有效地识别旁路电容器中存在的损耗，从而解决了当大电容器并联连接到小电容器时小电容器不可检测的问题。

2. 发明申请

US20110055631A1 PLUGGABLE ERROR DETECTION BOARD AND MOTHERBOARD ERROR DETECTION SYSTEM CONTAINING THE SAME 有权
标题翻译：可插拔错误检测板和包含其的主板错误检测系统
公开(公告)号：US20110055631A1
公开(公告)日：2011-03-03
申请号：US12611127
申请日：2009-11-03
申请人： Chih-Jen CHIN , Meng-Sen CHOU , Ying-Fan CHIANG , Chien-Chih CHANG
发明人： Chih-Jen CHIN , Meng-Sen CHOU , Ying-Fan CHIANG , Chien-Chih CHANG
IPC分类号： G06F11/00 , G06F11/22
CPC分类号： G06F11/2284
摘要： A motherboard error detection system includes a pluggable error detection board and a motherboard having a boot management chip. When the motherboard enters a device-driven status from a standby status, the boot management chip is used to manage power-on timings of different voltage sources; to collect a plurality of sets of status information; and to check whether the sets of status information and the power-on timings have errors. The pluggable error detection board includes an interpreting unit, a message-reading interface and a connector which is pluggably disposed on the motherboard. When the boot management chip notifies the pluggable error detection board to read an error message, the interpreting unit converts the error message to human-readable information, and the human-readable information is outputted through the message-reading interface.
摘要翻译：主板错误检测系统包括可插拔错误检测板和具有引导管理芯片的主板。当主板从待机状态进入设备驱动状态时，引导管理芯片用于管理不同电压源的上电时间; 收集多组状态信息; 并检查状态信息和开机定时是否有错误。可插拔错误检测板包括解释单元，消息读取界面和可插拔地设置在主板上的连接器。当引导管理芯片通知可插拔错误检测板读取错误消息时，解释单元将错误消息转换为人类可读取的信息，并通过消息读取界面输出人类可读取的信息。

3. 发明申请

US20120137027A1 SYSTEM AND METHOD FOR MONITORING INPUT/OUTPUT PORT STATUS OF PERIPHERAL DEVICES 审中-公开
标题翻译：用于监测外围设备的输入/输出端口状态的系统和方法
公开(公告)号：US20120137027A1
公开(公告)日：2012-05-31
申请号：US13070836
申请日：2011-03-24
申请人： Quan-Jie Zheng , Chih-Jen Chin , Ya-Jing Fan , Chih-Feng Chen
发明人： Quan-Jie Zheng , Chih-Jen Chin , Ya-Jing Fan , Chih-Feng Chen
IPC分类号： G06F3/00
CPC分类号： G06F11/3041 , G06F11/3055 , G06F11/3068
摘要： A system and method for monitoring an input/output port status of peripheral devices are used for monitoring an operating status of each peripheral device of a main board. The system includes at least one peripheral device, a complex programmable logic device (CPLD), and an output apparatus. The CPLD is electrically connected to the peripheral devices. The CPLD further includes a protocol conversion unit and multiple data registers. The protocol conversion unit converts an operating status of the CPLD or the peripheral devices into device status information. The data register is used for storing the device status information. The output apparatus is electrically connected to the CPLD. The output apparatus is used for displaying the device status information in the data register. A user can observe the operating status of each of the peripheral devices of the main board conveniently.
摘要翻译：用于监视外围设备的输入/输出端口状态的系统和方法用于监控主板的每个外围设备的操作状态。该系统包括至少一个外围设备，复杂可编程逻辑器件（CPLD）和输出设备。 CPLD电连接到外围设备。 CPLD还包括协议转换单元和多个数据寄存器。协议转换单元将CPLD或外围设备的操作状态转换为设备状态信息。数据寄存器用于存储设备状态信息。输出装置电连接到CPLD。输出装置用于在数据寄存器中显示设备状态信息。用户可以方便地观察主板各外围设备的运行状态。

4. 发明申请

US20100301886A1 TEST BOARD 有权
标题翻译：测试板
公开(公告)号：US20100301886A1
公开(公告)日：2010-12-02
申请号：US12505545
申请日：2009-07-20
申请人： Chih-Jen CHIN , Chun-Hao CHU , Ting-Hong WANG , Sheng-Yuan TSAI
发明人： Chih-Jen CHIN , Chun-Hao CHU , Ting-Hong WANG , Sheng-Yuan TSAI
IPC分类号： G01R31/02
CPC分类号： G01R31/026
摘要： A test board is provided. The test board includes a power connecting interface, diode modules, a power module a detecting module, and a processor. The power connecting interface includes power pins, wherein each of the power pins is electrically connected to a motherboard power socket to receive a power signal. Each of the diode modules is electrically connected to one of the power pins and includes at least one diode. The power module is electrically connected to the diode modules to receive the power signal through each of the diode modules. The detection module is electrically connected to points between the diode modules and the power connecting interface to generate a detection result according to the voltage between each diode module and the power connecting interface. The processor is used to determine the connecting state between the power pin and the corresponding motherboard power socket according to the detection result.
摘要翻译：提供测试板。测试板包括电源连接接口，二极管模块，电源模块，检测模块和处理器。电源连接接口包括电源引脚，其中每个电源引脚电连接到母板电源插座以接收电源信号。每个二极管模块电连接到一个电源引脚并且包括至少一个二极管。电源模块电连接到二极管模块以通过每个二极管模块接收电力信号。检测模块电连接到二极管模块和电源连接接口之间的点，以根据每个二极管模块和电源连接接口之间的电压产生检测结果。处理器用于根据检测结果确定电源引脚和相应的主板电源插座之间的连接状态。

5. 发明申请

US20120131385A1 TESTING MEHTOD FOR UNIT UNDER TEST 审中-公开
标题翻译：测试仪器测试
公开(公告)号：US20120131385A1
公开(公告)日：2012-05-24
申请号：US12981190
申请日：2010-12-29
申请人： CHIH-JEN CHIN , Lien-Feng Chen
发明人： CHIH-JEN CHIN , Lien-Feng Chen
IPC分类号： G06F11/26
CPC分类号： G06F11/2284 , G06F11/263
摘要： A testing method for a unit under test is provided. At least one unit under test is electrically connected to a testing machine. The testing machine creates a test script and executes the test script, so as to perform a non-operating system (OS) test and an OS test on the unit under test, and the testing machine is capable of combining the testing results, so a testing process is simplified, a test time is shortened, and test accuracy is improved.
摘要翻译：提供了被测单元的测试方法。至少一个被测单元与测试机电连接。测试机器创建测试脚本并执行测试脚本，以便对被测单元执行非操作系统（OS）测试和OS测试，并且测试机器能够组合测试结果，因此测试过程简化，测试时间缩短，测试精度提高。

6. 发明授权

US08074114B2 Motherboard error detection system 有权
标题翻译：主板错误检测系统
公开(公告)号：US08074114B2
公开(公告)日：2011-12-06
申请号：US12611127
申请日：2009-11-03
申请人： Chih-Jen Chin , Meng-Sen Chou , Ying-Fan Chiang , Chien-Chih Chang
发明人： Chih-Jen Chin , Meng-Sen Chou , Ying-Fan Chiang , Chien-Chih Chang
IPC分类号： G06F11/00
CPC分类号： G06F11/2284
摘要： A motherboard error detection system includes a pluggable error detection board and a motherboard having a boot management chip. When the motherboard enters a device-driven status from a standby status, the boot management chip is used to manage power-on timings of different voltage sources; to collect a plurality of sets of status information; and to check whether the sets of status information and the power-on timings have errors. The pluggable error detection board includes an interpreting unit, a message-reading interface and a connector which is pluggably disposed on the motherboard. When the boot management chip notifies the pluggable error detection board to read an error message, the interpreting unit converts the error message to human-readable information, and the human-readable information is outputted through the message-reading interface.
摘要翻译：主板错误检测系统包括可插拔错误检测板和具有引导管理芯片的主板。当主板从待机状态进入设备驱动状态时，引导管理芯片用于管理不同电压源的上电时间; 收集多组状态信息; 并检查状态信息和开机定时是否有错误。可插拔错误检测板包括解释单元，消息读取界面和可插拔地设置在主板上的连接器。当引导管理芯片通知可插拔错误检测板读取错误消息时，解释单元将错误消息转换为人类可读取的信息，并通过消息读取界面输出人类可读取的信息。

7. 发明申请

US20100049903A1 RECORDING SYSTEM AND DATA RECORDING METHOD 审中-公开
标题翻译：记录系统和数据记录方法
公开(公告)号：US20100049903A1
公开(公告)日：2010-02-25
申请号：US12258832
申请日：2008-10-27
申请人： Chih-Jen Chin , Sheng-Yuan Tsai
发明人： Chih-Jen Chin , Sheng-Yuan Tsai
IPC分类号： G06F12/02
CPC分类号： G11C16/102
摘要： A recording method for writing data into an electrically erasable programmable read-only memory is disclosed, in which the memory has already been electrically connected to a controller through a logic device. The method sets the logic devices for the first time to disconnect the memory from the controller, and set the logic devices for the second time to write setting data required by the controller into the memory. After that, the method reads out the setting data stored in the memory to confirm the writing of the setting data, and connects the memory to the controller again.
摘要翻译：公开了一种将数据写入电可擦除可编程只读存储器的记录方法，其中存储器已经通过逻辑器件电连接到控制器。该方法首次将逻辑设备设置为断开存储器与控制器的连接，并将逻辑设备第二次设置为将控制器所需的设置数据写入存储器。之后，该方法读出存储在存储器中的设置数据，以确认设置数据的写入，并再次将存储器连接到控制器。

8. 发明申请

US20090189637A1 Machine for programming on-board chipsets 审中-公开
标题翻译：用于编程板载芯片的机器
公开(公告)号：US20090189637A1
公开(公告)日：2009-07-30
申请号：US12010725
申请日：2008-01-29
申请人： Chih-Jen Chin , Sheng-Yuan Tsai
发明人： Chih-Jen Chin , Sheng-Yuan Tsai
IPC分类号： H03K19/173
CPC分类号： G11C16/102
摘要： The present invention discloses a machine for programming on-board chipsets, wherein the on-board chipsets means that some chipsets are mounted on a circuit board, and the circuit board has a plurality of input pads electrically connected to each chipset individually. The machine comprises a platform, a number of programming modules and an IC programming burner in which the platform faces a surface of the circuit board having the input pads, the programming modules disposed movably on the platform separately extends a number of output pins outwardly so that for connecting electrically an input pad as contacting the input pad, and the IC programming burner electrically connected to each of the programming modules separately distributes a set of programming codes into each programming module when the output pins electrically connect to the input pads.
摘要翻译：本发明公开了一种用于对板上芯片组进行编程的机器，其中板载芯片组意味着一些芯片组安装在电路板上，并且电路板具有分别与每个芯片组电连接的多个输入焊盘。该机器包括平台，多个编程模块和IC编程燃烧器，其中平台面向具有输入焊盘的电路板的表面，可移动地设置在平台上的编程模块分别向外延伸多个输出销，使得用于在接触输入焊盘时电连接输入焊盘，并且当连接到每个编程模块的IC编程器将输出引脚电连接到输入焊盘时，将一组编程代码单独地分配到每个编程模块中。

9. 发明申请

US20120137179A1 PROCESSING SYSTEM FOR MONITORING POWER-ON SELF-TEST INFORMATION 审中-公开
标题翻译：用于监控上电自检信息的处理系统
公开(公告)号：US20120137179A1
公开(公告)日：2012-05-31
申请号：US13070901
申请日：2011-03-24
申请人： Chih-Jen Chin , Xue-Shan Han , Ya-Jing Fan , Chih-Feng Chen
发明人： Chih-Jen Chin , Xue-Shan Han , Ya-Jing Fan , Chih-Feng Chen
IPC分类号： G06F11/22
CPC分类号： G06F11/2284
摘要： A processing system for monitoring the power-on self-test information is used for monitoring an operating state of a complex programmable logic device (CPLD) of a main board. The processing system includes a basic input/output system (BIOS) device, a CPLD and a monitoring device. The BIOS device sends power-on self-test information at a first frequency. The CPLD is electrically connected to the BIOS device. The CPLD further includes a first in first out (FIFO) register, and the FIFO register is used for storing the received power-on self-test information. The CPLD sends the power-on self-test information stored in the FIFO register at a second frequency. The monitoring device is electrically connected to the CPLD. The monitoring device is used for receiving the power-on self-test information sent from the CPLD.
摘要翻译：用于监视上电自检信息的处理系统用于监视主板的复杂可编程逻辑器件（CPLD）的工作状态。处理系统包括基本输入/输出系统（BIOS）设备，CPLD和监视设备。 BIOS设备以第一个频率发送开机自检信息。 CPLD电连接到BIOS设备。 CPLD进一步包括先进先出（FIFO）寄存器，FIFO寄存器用于存储接收到的开机自检信息。 CPLD以第二个频率发送存储在FIFO寄存器中的上电自检信息。监控设备电连接到CPLD。监控设备用于接收从CPLD发送的开机自检信息。

10. 发明申请

US20130162273A1 TESTING DEVICE 审中-公开
标题翻译：测试设备
公开(公告)号：US20130162273A1
公开(公告)日：2013-06-27
申请号：US13433744
申请日：2012-03-29
申请人： Chih-Jen CHIN , Pei-Lun HUANG
发明人： Chih-Jen CHIN , Pei-Lun HUANG
IPC分类号： G01R31/00
CPC分类号： G11C29/56 , G01R31/31721 , G11C11/40
摘要： A testing device comprising a power unit, a storage unit, and a controlling unit is mentioned. The power unit is adapted to provide different voltages. The storage unit is adapted to store a power sequence table and a simulation signal generating table. The controlling unit couples with the power unit and the storage unit, wherein the controlling unit is adapted to provide power sequence controlling signals according to the power sequence table, and the power unit is adapted to provide the voltages to the unit under test according to the power sequence controlling signals. The controlling unit is adapted to provide a simulation signal to the unit under test according to the simulation signal generating table, and the controlling unit is adapted to receive state signals generated by the unit under test in response to the voltages and the simulation signal.
摘要翻译：提到了包括动力单元，存储单元和控制单元的测试装置。电源单元适用于提供不同的电压。存储单元适于存储功率序列表和模拟信号产生表。所述控制单元与所述功率单元和所述存储单元耦合，其中所述控制单元适于根据所述功率顺序表提供功率序列控制信号，并且所述功率单元适于根据所述功率单元和所述存储单元向所述被测单元提供所述电压功率序列控制信号。控制单元适于根据模拟信号产生表向被测单元提供模拟信号，并且该控制单元适于接收由该电压和模拟信号响应的被测单元产生的状态信号。

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