专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07920083B2 Column-parallel sigma-delta analog-to-digital conversion with gain and offset control 有权
标题翻译：具有增益和偏移控制的列并行Σ-Δ模数转换
公开(公告)号：US07920083B2
公开(公告)日：2011-04-05
申请号：US12465476
申请日：2009-05-13
申请人： Christian Boemler
发明人： Christian Boemler
IPC分类号： H03M3/00
CPC分类号： H03M1/0604 , H03M1/123
摘要： A sigma-delta modulation sensing circuit and an analog-to-digital converter for an imager that eliminate the erroneous conversion of non-zero analog voltages to zero digital voltages is provided. The sensing circuit includes an offset branch that allows input of an offset voltage that is at least as large as a negative channel-specific offset found in a pixel signal voltage. The sensing circuit also includes a regulation branch based on a reference voltage common across multiple columns of an imager. The regulation branch has an adjustable resistance that is modulated during the sensing operation, which creates an adjustment current that is applied during the sensing operation to a reset signal. The sensing circuit and analog-to-digital converter generate digital code based on the difference between the reset voltage and the summed offset and pixel signal voltage.
摘要翻译：提供了一种Σ-Δ调制感测电路和用于成像器的模 - 数转换器，其消除非零模拟电压到零数字电压的错误转换。感测电路包括偏移分支，其允许输入至少与像素信号电压中发现的负通道特定偏移一样大的偏移电压。感测电路还包括基于在成像器的多列共同的参考电压的调节分支。调节分支具有在感测操作期间调制的可调电阻，这产生在感测操作期间施加到复位信号的调节电流。感测电路和模数转换器基于复位电压和总和偏移和像素信号电压之间的差异产生数字代码。

2. 发明授权

US07768562B2 Method, apparatus and system providing imager vertical binning and scaling using column parallel sigma-delta digital conversion 有权
标题翻译：使用列并行Σ-Δ数字转换的方法，装置和系统提供成像器垂直分档和缩放
公开(公告)号：US07768562B2
公开(公告)日：2010-08-03
申请号：US11545063
申请日：2006-10-10
申请人： Christian Boemler
发明人： Christian Boemler
IPC分类号： H04N3/14 , H04N5/335 , H03M3/00 , H01L27/00
CPC分类号： H04N9/045 , H04N5/3458 , H04N5/347
摘要： A method, apparatus and system are disclosed for digitizing a plurality of analog pixel signals of a pixel array in a manner which produces a digital signal representing the combination of said plurality of analog pixel signals. A readout architecture performs at least some binning and/or scaling operations in the readout and analog to digital conversion circuits relieving an image processor from the task of performing these operations.
摘要翻译：公开了一种用于以产生表示所述多个模拟像素信号的组合的数字信号的方式数字化像素阵列的多个模拟像素信号的方法，装置和系统。读出架构在读出和模数转换电路中执行至少一些分档和/或缩放操作，以使图像处理器免于执行这些操作的任务。

3. 发明申请

US20090244039A1 REDUNDANCY IN COLUMN PARALLEL OR ROW ARCHITECTURES 有权
标题翻译：在平行或平行架构中的冗余
公开(公告)号：US20090244039A1
公开(公告)日：2009-10-01
申请号：US12476757
申请日：2009-06-02
申请人： Christian Boemler
发明人： Christian Boemler
IPC分类号： G06F3/038
CPC分类号： H04N5/378 , H04N5/335 , H04N5/361 , H04N5/3658 , H04N5/374
摘要： A column circuitry architecture for an imager includes redundant column or row circuits. The column or row circuitry includes a number of redundant column or row circuits. Each column or row circuit include circuitry for controllably coupling the column or row circuit to one of plural signal lines from an array of pixels. A control mechanism is used to select a configuration of plural column or row circuits in the column or row circuitry. In this manner, some column or row circuits are decoupled from the pixel in favor of other column or row circuits. The decoupled column or row circuits may include defective or noisy circuits.
摘要翻译：用于成像器的列电路架构包括冗余列或行电路。列或行电路包括多个冗余列或行电路。每列或行电路包括用于将列或行电路可控地耦合到来自像素阵列的多条信号线之一的电路。控制机构用于选择列或行电路中的多个列或行电路的配置。以这种方式，有利于其他列或行电路的一些列或行电路与像素去耦。解耦的列或行电路可以包括有缺陷或噪声电路。

4. 发明申请

US20090166515A1 MULTI-POINT CORRELATED SAMPLING FOR IMAGE SENSORS 审中-公开
标题翻译：多点相关采样图像传感器
公开(公告)号：US20090166515A1
公开(公告)日：2009-07-02
申请号：US12335249
申请日：2008-12-15
申请人： Christian Boemler
发明人： Christian Boemler
IPC分类号： H01L27/146
CPC分类号： H04N5/3575 , H04N5/3592
摘要： An improved passive pixel sensor (PPS) circuit comprising a correlated sampling circuit and method that integrates pixel charge leakage onto an integrating amplifier during sampling periods. An integrator circuit is provided for integrating PPS pixel charges received via a column line, and correlated sampling circuit is provided for the removal of kTC noise and dark integration. A multi-point sampling of the output of the integrator is provided wherein at least a first and second correlated sample are used to detect the charge integration from the column line leakages, and at least a third sample is used to detect the PPS signal after pixel readout. The correlated sampling method is employed to remove kTC noise and dark integration from the PPS signal.
摘要翻译：一种改进的无源像素传感器（PPS）电路，包括在采样周期内将像素电荷泄漏积分到积分放大器上的相关采样电路和方法。提供积分电路，用于对通过列线接收的PPS像素电荷进行积分，并提供相关采样电路，用于去除kTC噪声和暗积分。提供积分器的输出的多点采样，其中使用至少第一和第二相关样本来检测来自列线泄漏的电荷积分，并且使用至少第三采样来检测像素之后的PPS信号读出。采用相关采样方法从PPS信号中去除kTC噪声和暗积分。

5. 发明授权

US07545300B2 Column-parallel sigma-delta analog-to-digital conversion with gain and offset control 有权
标题翻译：具有增益和偏移控制的列并行Σ-Δ模数转换
公开(公告)号：US07545300B2
公开(公告)日：2009-06-09
申请号：US11806834
申请日：2007-06-04
申请人： Christian Boemler
发明人： Christian Boemler
IPC分类号： H03M3/00
CPC分类号： H03M1/0604 , H03M1/123
摘要： A sigma-delta modulation sensing circuit and an analog-to-digital converter for an imager that eliminate the erroneous conversion of non-zero analog voltages to zero digital voltages is provided. The sensing circuit includes an offset branch that allows input of an offset voltage that is at least as large as a negative channel-specific offset found in a pixel signal voltage. The sensing circuit also includes a regulation branch based on a reference voltage common across multiple columns of an imager. The regulation branch has an adjustable resistance that is modulated during the sensing operation, which creates an adjustment current that is applied during the sensing operation to a reset signal. The sensing circuit and analog-to-digital converter generate digital code based on the difference between the reset voltage and the summed offset and pixel signal voltage.
摘要翻译：提供了一种Σ-Δ调制感测电路和用于成像器的模 - 数转换器，其消除非零模拟电压到零数字电压的错误转换。感测电路包括偏移分支，其允许输入至少与像素信号电压中发现的负通道特定偏移一样大的偏移电压。感测电路还包括基于在成像器的多列共同的参考电压的调节分支。调节分支具有在感测操作期间调制的可调电阻，这产生在感测操作期间施加到复位信号的调节电流。感测电路和模数转换器基于复位电压和总和偏移和像素信号电压之间的差异产生数字代码。

6. 发明授权

US07544921B2 Linear distributed pixel differential amplifier having mirrored inputs 有权
标题翻译：具有镜像输入的线性分布式像素差分放大器
公开(公告)号：US07544921B2
公开(公告)日：2009-06-09
申请号：US11334626
申请日：2006-01-19
申请人： Christian Boemler
发明人： Christian Boemler
IPC分类号： H03F3/08
CPC分类号： H04N5/3745
摘要： A pixel circuit that partially incorporates an associated column amplifier into the pixel circuitry. By incorporating part of a mirrored amplifier into the pixel, noise from the pixel is reduced.
摘要翻译：像素电路，其将相关联的列放大器部分地并入到像素电路中。通过将一部分镜像放大器并入到像素中，来自像素的噪声减小。

7. 发明申请

US20080084341A1 Method, apparatus and system providing imager vertical binning and scaling using column parallel sigma-delta digital conversion 有权
标题翻译：使用列并行Σ-Δ数字转换的方法，装置和系统提供成像器垂直分档和缩放
公开(公告)号：US20080084341A1
公开(公告)日：2008-04-10
申请号：US11545063
申请日：2006-10-10
申请人： Christian Boemler
发明人： Christian Boemler
IPC分类号： H03M3/00
CPC分类号： H04N9/045 , H04N5/3458 , H04N5/347
摘要： A method, apparatus and system are disclosed for digitizing a plurality of analog pixel signals of a pixel array in a manner which produces a digital signal representing the combination of said plurality of analog pixel signals. A readout architecture performs at least some binning and/or scaling operations in the readout and analog to digital conversion circuits relieving an image processor from the task of performing these operations.
摘要翻译：公开了一种用于以产生表示所述多个模拟像素信号的组合的数字信号的方式数字化像素阵列的多个模拟像素信号的方法，装置和系统。读出架构在读出和模数转换电路中执行至少一些分档和/或缩放操作，以使图像处理器免于执行这些操作的任务。

8. 发明申请

US20060239068A1 Static random access memory cell 有权
公开(公告)号：US20060239068A1
公开(公告)日：2006-10-26
申请号：US11113365
申请日：2005-04-21
申请人： Christian Boemler
发明人： Christian Boemler
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C11/412 , G11C8/16
摘要： A static random access memory (SRAM) cell having an inverter and a tri-state inverter. An input of the inverter is coupled to an output of the tri-state inverter and an output of the inverter is coupled to an input of the tri-state inverter. The tri-state inverter has an enable node to which a read signal is applied and is configured to generate an output signal that is the complement of an input signal in response to an active read signal. The SRAM cell further includes an access transistor having a first node coupled to the output of the tri-state inverter and having a second node coupled to the digit line. The access transistor is configured to couple the first and second nodes in response to an active access signal applied to its gate.

9. 发明申请

US20060145906A1 Minimized SAR-type column-wide ADC for image sensors 有权
公开(公告)号：US20060145906A1
公开(公告)日：2006-07-06
申请号：US11293262
申请日：2005-12-05
申请人： Christian Boemler
发明人： Christian Boemler
IPC分类号： H03M1/12
CPC分类号： H03M1/403 , H03M1/123 , H04N5/374 , H04N5/378
摘要： An improved analog-to-digital converter wherein a minimal amount of circuitry is provided for conversion of an analog signal to a series of digital bits. A comparator is provided for generating digital values to which the digital bits correspond. A digital-to-analog converter is provided for generating, via successive approximation, a feedback analog signal based on bits previously generated by the comparator. The analog-to-digital converter compares the feedback analog signal to the input analog signal, and based on the comparison generates a digital value that corresponds to a digital bit. In the method of the invention, an analog signal is converted to a digital value using the analog-to-digital converter, and a digital-to-analog converter comprising two capacitors and a reference selector generates, via successive approximation, a feedback analog signal that is applied to a comparator for comparison to the input analog signal being digitized.

10. 发明授权

US07061413B2 Analog to digital conversion with offset cancellation 失效
标题翻译：具有偏移消除的模数转换
公开(公告)号：US07061413B2
公开(公告)日：2006-06-13
申请号：US10925171
申请日：2004-08-25
申请人： Christian Boemler
发明人： Christian Boemler
IPC分类号： H03M1/10 , H03M1/12
CPC分类号： H03M1/1023 , H03M1/123 , H03M1/40
摘要： An analog to digital conversion circuit includes a voltage-to-charge converter coupled to a charge integrator and a comparator. The voltage-to-charge converter is coupled to, and converts the voltage of, an analog signal or one of a set of reference voltages, into an equivalent charge. The charge integrator then adds or subtracts that equivalent charge in an iterative manner based on an output of the comparator. The initial charge of the charge integrator is based on a previous conversion. When plural analog to digital conversion circuits are used the initial charge in each such circuit may be different, as each initial charge serves to automatically compensate for any offset in the output of the circuit.
摘要翻译：模数转换电路包括耦合到电荷积分器和比较器的电压 - 电荷转换器。电压 - 电荷转换器耦合到模拟信号或一组参考电压中的一个电压并将其转换为等效电荷。然后，电荷积分器基于比较器的输出以迭代方式加或减去该等效电荷。电荷积分器的初始电荷基于之前的转换。当使用多个模数转换电路时，每个这样的电路中的初始电荷可以不同，因为每个初始电荷用于自动补偿电路的输出中的任何偏移。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式