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    • 3. 发明申请
    • Mismatch Error Reduction Method and System for STT MRAM
    • STT MRAM的不匹配误差减少方法和系统
    • US20140063923A1
    • 2014-03-06
    • US13605693
    • 2012-09-06
    • Mihail JefremowWolf AllersJan OtterstedtChristian PetersThomas Kern
    • Mihail JefremowWolf AllersJan OtterstedtChristian PetersThomas Kern
    • G11C7/06G11C11/16
    • G11C11/1673
    • The invention relates to methods and systems for reading a memory cell and in particular, an STT MRAM. In accordance with one aspect of the invention, a method for reading a memory cell includes combining a cell current from a memory cell with a reference current from a reference source to create an average current, enabling the average current to flow through a first mirror transistor in a sense path and a second mirror transistor in a reference path, storing the current mismatch on a capacitor coupled to the gates of the first mirror transistor and the second mirror transistor, disconnecting the memory cell from the reference path and disconnecting the reference source from the sense path, enabling the cell current only to flow through the sense path, and determining the output level of the memory cell.
    • 本发明涉及用于读取存储器单元,特别是STT MRAM的方法和系统。 根据本发明的一个方面,一种用于读取存储单元的方法包括将来自存储单元的单元电流与来自参考源的参考电流组合以产生平均电流,使平均电流能够流过第一镜像晶体管 在参考路径中的感测路径和第二镜像晶体管中,将电流失配存储在耦合到第一镜面晶体管和第二镜像晶体管的栅极的电容器上,将存储器单元与参考路径断开并将参考源与 感测路径,使得电池电流仅能够流过感测路径,并且确定存储器单元的输出电平。
    • 7. 发明申请
    • NON-VOLATILE MEMORY WITH PREDICTIVE PROGRAMMING
    • 具有预测编程的非易失性存储器
    • US20110103150A1
    • 2011-05-05
    • US12610781
    • 2009-11-02
    • Nigel ChanWolf AllersMichael BolluDimitri LebedevJan OtterstedtChristian Peters
    • Nigel ChanWolf AllersMichael BolluDimitri LebedevJan OtterstedtChristian Peters
    • G11C16/04G11C16/06
    • G11C16/349G11C16/0483G11C16/06
    • A method of operating an integrated circuit includes applying at least one first programming pulse to a plurality of non-volatile memory cells to adjust a level of a storage parameter of each of the non-volatile memory cells, the at least one first programming pulse defined by a plurality of pulse parameters each having a fixed valued, and determining a fail count by measuring the number of non-volatile memory cells of the plurality of non-volatile memory cells having a storage parameter level exceeding a verify level. The method further includes determining a change in an programming behavior of the plurality of non-volatile memory cells based on the fail count, adjusting a value of at least one pulse parameter of at least one second programming pulse defined by the plurality of pulse parameters to a desired value based on the change in programming behavior, and applying the at least one second programming pulse to the plurality non-volatile memory cells.
    • 操作集成电路的方法包括将至少一个第一编程脉冲施加到多个非易失性存储器单元以调整每个非易失性存储单元的存储参数的电平,所述至少一个第一编程脉冲被定义 通过多个具有固定值的脉冲参数,并且通过测量具有超过验证电平的存储参数电平的多个非易失性存储器单元的非易失性存储器单元的数量来确定故障计数。 该方法还包括基于故障计数确定多个非易失性存储器单元的编程行为的变化,将由多个脉冲参数定义的至少一个第二编程脉冲的至少一个脉冲参数的值调整为 基于编程行为的变化的期望值,以及将所述至少一个第二编程脉冲应用于所述多个非易失性存储器单元。