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1. 发明授权

US08831671B2 Automated parameter adjustment to compensate self adjusting transmit power and sensitivity level at the node B 有权
标题翻译：自动参数调整，以补偿节点B的自调节发射功率和灵敏度级别
公开(公告)号：US08831671B2
公开(公告)日：2014-09-09
申请号：US13621674
申请日：2012-09-17
申请人： Aziz Gholmieh , Farhad Meshkati , Mehmet Yavuz , Siddharth Mohan , Christophe Chevallier
发明人： Aziz Gholmieh , Farhad Meshkati , Mehmet Yavuz , Siddharth Mohan , Christophe Chevallier
IPC分类号： H04B7/00 , H04W52/24 , H04W52/10 , H04W52/36
CPC分类号： H04W52/10 , H04W52/244 , H04W52/246 , H04W52/367
摘要： A small base node such as a Home Base Node (HNB), or femto cell, may reduce its transmit power in order to prevent co-channel or adjacent channel interference, or to limit its coverage area. Once the power is set, the HNB signal to a served Home User Equipment (HUE) its transmit Common Pilot Channel (CPICH) transmit power for accurate path loss estimation. When this power is outside of the permissible range, the HNB adjusts other parameters (such as Random Access Channel (RACH) constant value) to compensate for the error in signaled CPICH power, and thus compensate in that process the error in determining path loss. Similarly, if the uplink sensitivity is adjusted, to prevent interference, parameters would also be adjusted and signaled to the HUE to reflect the link imbalance.
摘要翻译：诸如家庭基站节点（HNB）或毫微微小区之类的小型基站节点可以降低其发射功率，以防止同信道或相邻信道干扰，或限制其覆盖区域。一旦功率被设置，HNB信号到服务的家庭用户设备（HUE），其发射公共导频信道（CPICH）发送功率用于精确的路径损耗估计。当该功率超出允许范围时，HNB调整其他参数（如随机接入信道（RACH）常数值）来补偿信令CPICH功率中的误差，从而在该过程中补偿确定路径损耗的误差。类似地，如果调整上行链路灵敏度，为了防止干扰，参数也将被调整并发出信号到HUE以反映链路不平衡。

2. 发明授权

US08305796B2 Access signal adjustment circuits and methods for memory cells in a cross-point array 有权
标题翻译：交叉点阵列中存储单元的访问信号调整电路和方法
公开(公告)号：US08305796B2
公开(公告)日：2012-11-06
申请号：US13425247
申请日：2012-03-20
申请人： Christophe Chevallier , Chang Hua Siau
发明人： Christophe Chevallier , Chang Hua Siau
IPC分类号： G11C11/00
CPC分类号： G11C13/0033 , G11C11/21 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0069
摘要： Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, such as memory implemented in third dimensional memory technology formed BEOL directly on top of a FEOL substrate that includes data access circuitry. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements disposed among word lines and subsets of bit lines, and an access signal generator. The access signal generator can be configured to modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. The modified magnitude can be a function of the position of the resistive memory element in the cross-point array.
摘要翻译：本发明的实施例一般涉及半导体和存储器技术，更具体地涉及系统，集成电路和方法，用于产生存取信号以促进存储器元件的按比例排列的存储器操作，诸如在形成的第三维存储器技术中实现的存储器直接位于包含数据访问电路的FEOL基板之上。在至少一些实施例中，非易失性存储器件可以包括具有布置在字线和位线子集之间的电阻性存储器元件的交叉点阵列和存取信号发生器。访问信号发生器可被配置为修改信号的大小以产生用于信号访问与字线和位线子集相关联的电阻性存储器元件的修改幅度。修改的幅度可以是交叉点阵列中的电阻性存储元件的位置的函数。

3. 发明申请

US20120264416A1 SELECTIVE STATE TRANSITIONS OF A USER EQUIPMENT WITHIN A WIRELESS COMMUNICATIONS SYSTEM 失效
标题翻译：用户设备在无线通信系统中的选择状态转换
公开(公告)号：US20120264416A1
公开(公告)日：2012-10-18
申请号：US13086534
申请日：2011-04-14
申请人： Francesco Pica , Etienne Francois Chaponniere , Christophe Chevallier , Andrea Garavaglia , Aziz Gholmieh , Long Duan , Mukesh Kumar Mittal , Mustafa Saglam , Sunil Suresh Patil , Salil Sawhney , Rajasekar Arulprakasam , Jochen Hoidis
发明人： Francesco Pica , Etienne Francois Chaponniere , Christophe Chevallier , Andrea Garavaglia , Aziz Gholmieh , Long Duan , Mukesh Kumar Mittal , Mustafa Saglam , Sunil Suresh Patil , Salil Sawhney , Rajasekar Arulprakasam , Jochen Hoidis
IPC分类号： H04W24/00
CPC分类号： H04W52/0254 , H04W76/27 , Y02D70/1224 , Y02D70/1242 , Y02D70/1244 , Y02D70/1262 , Y02D70/23 , Y02D70/24
摘要： In an embodiment, a user equipment (UE) determines that a client application has entered a period of transmission inactivity whereby the UE will not be required to transmit data on behalf of the client application. The UE selectively transmits a transmission inactivity notification to an access network (AN) to notify the AN of the transmission inactivity period. The AN receives the transmission inactivity notification and determines to transition the UE from a first state to a second state based at least in part on the received transmission inactivity notification, the second state associated with lower-power consumption of the UE than the first state. The AN sends instructions to the UE to facilitate the transition of the UE from the first state to the second state. In another embodiment, the AN can send instructions to the UE to prohibit the UE from sending transmission inactivity notifications.
摘要翻译：在一个实施例中，用户设备（UE）确定客户端应用已经进入传输不活动的周期，由此UE将不需要代表客户端应用传输数据。 UE选择性地向接入网络（AN）发送传输不活动通知，以通知AN传输不活动时段。 AN接收传输不活动通知，并且确定至少部分地基于所接收的传输不活动通知将UE从第一状态转换到第二状态，与UE的低功耗相关的第二状态比第一状态。 AN向UE发送指令以促进UE从第一状态到第二状态的转换。在另一个实施例中，AN可以向UE发送指令以禁止UE发送传输不活动通知。

4. 发明授权

US08270193B2 Local bit lines and methods of selecting the same to access memory elements in cross-point arrays 有权
标题翻译：本地位线及其选择方法可以访问交叉点阵列中的存储器元件
公开(公告)号：US08270193B2
公开(公告)日：2012-09-18
申请号：US12657911
申请日：2010-01-29
申请人： Chang Hua Siau , Christophe Chevallier , Darrell Rinerson , Seow Fong Lim , Sri Rama Namala
发明人： Chang Hua Siau , Christophe Chevallier , Darrell Rinerson , Seow Fong Lim , Sri Rama Namala
IPC分类号： G11C5/02
CPC分类号： G11C5/025 , G11C5/02 , G11C8/00 , G11C11/00 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2213/77 , H01L21/82 , H01L27/2481 , H01L45/16
摘要： Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.
摘要翻译：实施例通常涉及半导体和存储器技术，更具体地，涉及用于实现存储器架构的系统，集成电路和方法，该存储器架构包括用于访问诸如基于第三维存储器技术的存储器元件的存储器元件的子集的本地位线。在至少一些实施例中，集成电路包括形成在逻辑层上方的交叉点存储器阵列。交叉点存储器阵列包括X线和Y线，其中至少一条Y线包括Y线部分的组。每个Y线部分可以与一组Y线部分内的其它Y线部分平行地布置。还包括设置在X线的子集和Y线部分的组之间的存储器元件。在一些实施例中，解码器被配置为从Y组部分组中选择Y线部分以访问存储器元件的子集。

5. 发明授权

US08139409B2 Access signal adjustment circuits and methods for memory cells in a cross-point array 有权
公开(公告)号：US08139409B2
公开(公告)日：2012-03-20
申请号：US12657895
申请日：2010-01-29
申请人： Christophe Chevallier , Chang Hua Siau
发明人： Christophe Chevallier , Chang Hua Siau
IPC分类号： G11C16/04
CPC分类号： G11C13/0033 , G11C11/21 , G11C13/0011 , G11C13/003 , G11C13/004 , G11C13/0069
摘要： Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, such as memory implemented in third dimensional memory technology formed BEOL directly on top of a FEOL substrate that includes data access circuitry. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements disposed among word lines and subsets of bit lines, and an access signal generator. The access signal generator can be configured to modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. The modified magnitude can be a function of the position of the resistive memory element in the cross-point array.

6. 发明授权

US08031545B2 Low read current architecture for memory 有权
标题翻译：低读取存储体系结构
公开(公告)号：US08031545B2
公开(公告)日：2011-10-04
申请号：US12799168
申请日：2010-04-19
申请人： Darrell Rinerson , Christophe Chevallier , Chang Hua Siau
发明人： Darrell Rinerson , Christophe Chevallier , Chang Hua Siau
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/22 , G11C13/0007 , G11C13/0026 , G11C13/004 , G11C13/0061 , G11C13/02 , G11C2013/0054 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77
摘要： A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.
摘要翻译：用于存储器的低读取当前体系结构。允许交叉点存储器阵列的位线被选择的字线充电，直到确保存储器状态和参考电平之间的最小电压差。

7. 发明申请

US20110188281A1 Local bit lines and methods of selecting the same to access memory elements in cross-point arrays 有权
标题翻译：本地位线及其选择方法可以访问交叉点阵列中的存储器元件
公开(公告)号：US20110188281A1
公开(公告)日：2011-08-04
申请号：US12657911
申请日：2010-01-29
申请人： Chang Hua Siau , Christophe Chevallier , Darrell Rinerson , Seow Fong Lim , Sri Namala
发明人： Chang Hua Siau , Christophe Chevallier , Darrell Rinerson , Seow Fong Lim , Sri Namala
IPC分类号： G11C5/02 , G11C11/00 , G11C8/00 , H01L21/82
CPC分类号： G11C5/025 , G11C5/02 , G11C8/00 , G11C11/00 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C13/0097 , G11C2213/77 , H01L21/82 , H01L27/2481 , H01L45/16
摘要： Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.
摘要翻译：实施例通常涉及半导体和存储器技术，更具体地，涉及用于实现存储器架构的系统，集成电路和方法，该存储器架构包括用于访问诸如基于第三维存储器技术的存储器元件的存储器元件的子集的本地位线。在至少一些实施例中，集成电路包括形成在逻辑层上方的交叉点存储器阵列。交叉点存储器阵列包括X线和Y线，其中至少一条Y线包括Y线部分的组。每个Y线部分可以与一组Y线部分内的其它Y线部分平行地布置。还包括设置在X线的子集和Y线部分的组之间的存储器元件。在一些实施例中，解码器被配置为从Y组部分组中选择Y线部分以访问存储器元件的子集。

8. 发明授权

US07978501B2 Method for contemporaneous margin verification and memory access for memory cells in cross-point memory arrays 有权
标题翻译：交叉点存储器阵列中存储单元的同期保证金验证和存储器访问的方法
公开(公告)号：US07978501B2
公开(公告)日：2011-07-12
申请号：US12927247
申请日：2010-11-09
申请人： Christophe Chevallier , Chang Hua Siau
发明人： Christophe Chevallier , Chang Hua Siau
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/5685 , G11C13/0007 , G11C13/0033 , G11C13/004 , G11C13/0061 , G11C16/3418 , G11C16/3431 , G11C2013/0054 , G11C2211/5634 , G11C2211/5646 , G11C2213/71 , G11C2213/77
摘要： Circuitry and methods for restoring data values in non-volatile memory are disclosed. An integrated circuit includes a memory access circuit and a sensing circuit configured to sense a data signal during a read operation to at least one two-terminal non-volatile cross-point memory array. Each memory array includes a plurality of two-terminal memory cells. A plurality of the memory arrays can be fabricated over the substrate and vertically stacked on one another. Further, the integrated circuit can include a margin manager circuit configured to manage a read margin for the two-terminal memory cells substantially during the read operation, thereby providing for contemporaneous read and margin determination operations. Stored data read from the two-terminal memory cells may have a value of the stored data restored (e.g., re-written to the same cell or another cell) if the value is not associated with a read margin (e.g., a hard programmed or hard erased state).
摘要翻译：公开了用于恢复非易失性存储器中的数据值的电路和方法。集成电路包括存储器访问电路和被配置为在至少一个两端非易失性交叉点存储器阵列的读取操作期间感测数据信号的感测电路。每个存储器阵列包括多个两端存储单元。可以在衬底上制造多个存储器阵列并且彼此垂直地堆叠。此外，集成电路可以包括边缘管理器电路，其被配置为基本上在读取操作期间管理两端存储器单元的读取余量，从而提供同时的读取和余量确定操作。从两端存储单元读取的存储数据可以具有恢复的存储数据的值（例如，重新写入同一单元或另一单元），如果该值不与读取余量相关联（例如，硬编程或硬擦除状态）。

9. 发明申请

US20110111752A1 METHODS AND APPARATUS FOR EVALUATING BASE STATION EFFICIENCY IN A NETWORK 失效
标题翻译：在网络中评估基站效率的方法和装置
公开(公告)号：US20110111752A1
公开(公告)日：2011-05-12
申请号：US12614271
申请日：2009-11-06
申请人： Amer Catovic , Christophe Chevallier , Mustafa Saglam
发明人： Amer Catovic , Christophe Chevallier , Mustafa Saglam
IPC分类号： H04W24/00
CPC分类号： H04W24/08 , Y02D70/1242 , Y02D70/1262 , Y02D70/142 , Y02D70/144 , Y02D70/146 , Y02D70/22
摘要： A method and apparatus evaluating base station efficiency in a network. The method may comprises: obtaining, from a plurality of base stations, cell performance measurements, wherein the cell performance measurements include a transmitted carrier power value and a dedicated channel (DCH) power value, generating a plurality of cell efficiency coefficients for each of the plurality of base stations by processing the obtained cell performance measurements, determining if at least one of the plurality of base stations is an inefficient base station from at least one of the plurality of cell efficiency coefficients, and transmitting at least one network modification suggestion, wherein the at least one network modification suggestion is based on the at least one of the plurality of cell efficiency coefficients used in determining the at least one inefficient base station.
摘要翻译：评估网络中基站效率的方法和装置。该方法可以包括：从多个基站获得小区性能测量，其中小区性能测量包括传输的载波功率值和专用信道（DCH）功率值，产生多个小区效率系数多个基站，通过处理所获得的小区性能测量，确定所述多个基站中的至少一个基站是否是所述多个小区效率系数中的至少一个的低效基站，以及发送至少一个网络修改建议，其中，所述至少一个网络修改建议基于用于确定所述至少一个低效率基站中的所述多个小区效率系数中的至少一个。

10. 发明申请

US20100202188A1 Low read current architecture for memory 有权
公开(公告)号：US20100202188A1
公开(公告)日：2010-08-12
申请号：US12799168
申请日：2010-04-19
申请人： Darrell Rinerson , Christophe Chevallier , Chang Hua Siau
发明人： Darrell Rinerson , Christophe Chevallier , Chang Hua Siau
IPC分类号： G11C11/00 , G11C7/00 , G11C7/06
CPC分类号： G11C7/12 , G11C7/22 , G11C13/0007 , G11C13/0026 , G11C13/004 , G11C13/0061 , G11C13/02 , G11C2013/0054 , G11C2213/11 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/77
摘要： A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.

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