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1. 发明授权

US07359453B1 System and method for transitioning between modulation formats in adjacent bursts triggering on ramps 有权
标题翻译：用于在斜坡上触发相邻脉冲串中的调制格式之间进行转换的系统和方法
公开(公告)号：US07359453B1
公开(公告)日：2008-04-15
申请号：US10985209
申请日：2004-11-10
申请人： Alexander Wayne Hietala , Christopher Truong Ngo
发明人： Alexander Wayne Hietala , Christopher Truong Ngo
IPC分类号： H04K1/02
CPC分类号： H04L27/0008
摘要： A modulation system and method are provided for transitioning between modulation formats in adjacent transmit bursts. The modulation system includes a data interface, first modulation circuitry operating according to a first modulation format, and second modulation circuitry operating according to a second modulation format. During a transition, a timing signal triggers ramp-down of an output power of a power amplifier amplifying modulated data for the first transmit burst. Upon receiving the timing signal, the data interface proceeds to provide a current symbol of data for the first transmit burst. Upon completion of the current symbol, the data interface delays data for a second transmit burst by a variable delay time prior to providing the data for the second transmit burst to the second modulation circuitry, and the second modulation circuitry is reset. Accordingly, a glitch caused by resetting the second modulation circuitry occurs before ramp-up for the second transmit burst.
摘要翻译：提供了用于在相邻发射脉冲串中的调制格式之间转换的调制系统和方法。调制系统包括数据接口，根据第一调制格式操作的第一调制电路和根据第二调制格式操作的第二调制电路。在转换期间，定时信号触发放大用于第一发射脉冲串的调制数据的功率放大器的输出功率的斜降。在接收到定时信号时，数据接口继续提供用于第一发送突发的数据的当前符号。在完成当前符号之后，数据接口在向第二调制电路提供用于第二发射脉冲串的数据之前，将可变延迟时间的第二发射脉冲串的数据延迟，并且第二调制电路被复位。因此，在第二发射脉冲串的斜坡上升之前发生由复位第二调制电路引起的毛刺。

2. 发明申请

US20120170690A1 AUTO CONFIGURABLE 2/3 WIRE SERIAL INTERFACE 有权
标题翻译：自动配置2/3线串行接口
公开(公告)号：US20120170690A1
公开(公告)日：2012-07-05
申请号：US13172371
申请日：2011-06-29
申请人： Christopher Truong Ngo , Roman Zbigniew Arkiszewski , Brad Hunkele
发明人： Christopher Truong Ngo , Roman Zbigniew Arkiszewski , Brad Hunkele
IPC分类号： H04L27/06
CPC分类号： H03F1/0227 , H03F1/0261 , H03F1/0277 , H03F3/195 , H03F3/211 , H03F3/245 , H03F3/602 , H03F3/72 , H03F2200/171 , H03F2200/222 , H03F2200/27 , H03F2200/318 , H03F2200/336 , H03F2200/387 , H03F2200/411 , H03F2200/414 , H03F2200/417 , H03F2200/451 , H03F2200/504 , H03F2200/534 , H03F2200/537 , H03F2200/541 , H03F2203/21106 , H03F2203/21142 , H03F2203/21157
摘要： An automatically configurable 2-wire/3-wire serial communications interface (AC23SCI), which includes start-of-sequence (SOS) detection circuitry and sequence processing circuitry, is disclosed. When the SOS detection circuitry is coupled to a 2-wire serial communications bus, the SOS detection circuitry detects an SOS of a received sequence based on a serial data signal and a serial clock signal. When the SOS detection circuitry is coupled to a 3-wire serial communications bus, the SOS detection circuitry detects the SOS of the received sequence based on a chip select (CS) signal. The SOS detection circuitry provides an indication of detection of the SOS to the sequence processing circuitry, which initiates processing of the received sequence using the serial data signal and the serial clock signal upon the detection of the SOS. As such, the AC23SCI automatically configures itself for operation with some 2-wire and some 3-wire serial communications buses without external intervention.
摘要翻译：公开了一种自动配置的2线/ 3线串行通信接口（AC23SCI），其包括序列启动（SOS）检测电路和序列处理电路。当SOS检测电路耦合到2线串行通信总线时，SOS检测电路基于串行数据信号和串行时钟信号检测接收序列的SOS。当SOS检测电路耦合到3线串行通信总线时，SOS检测电路基于芯片选择（CS）信号检测接收到的序列的SOS。 SOS检测电路提供对序列处理电路的SOS的检测的指示，该序列处理电路在检测到SOS时使用串行数据信号和串行时钟信号启动接收到的序列的处理。因此，AC23SCI自动配置自己的操作与一些2线和一些3线串行通信总线，无需外部干预。

3. 发明授权

US09325353B2 Architecture for a radio frequency front-end 有权
标题翻译：射频前端的架构
公开(公告)号：US09325353B2
公开(公告)日：2016-04-26
申请号：US13611620
申请日：2012-09-12
申请人： John Robert Siomkos , Jayanti Jaganatha Rao , Christopher Truong Ngo
发明人： John Robert Siomkos , Jayanti Jaganatha Rao , Christopher Truong Ngo
IPC分类号： H04B1/38 , H04B1/00
CPC分类号： H04B1/006
摘要： An architecture for a radio frequency (RF) front-end is disclosed. The architecture for the RF front-end includes a circuit module that includes a plurality of dies partitioned on the circuit module. A plurality of filter banks with individual ones of the plurality of filter banks disposed on each of the plurality of circuit dies is also included. Further included is a plurality of switches having individual ones of the plurality of switches coupled to corresponding ones of the plurality of filter banks and in at least one embodiment a control system is configured to open and close selected ones of the plurality of switches.
摘要翻译：公开了一种用于射频（RF）前端的架构。 RF前端的架构包括电路模块，其包括在电路模块上分隔的多个管芯。还包括多个滤波器组，其中设置在多个电路管芯中的每一个上的多个滤波器组中的单个滤波器组。还包括多个开关，其具有耦合到多个滤波器组中的相应开关的多个开关中的各个开关，并且在至少一个实施例中，控制系统被配置为打开和闭合多个开关中的选定开关。

4. 发明授权

US08983409B2 Auto configurable 2/3 wire serial interface 有权
标题翻译：可自动配置的2线/ 3线串行接口
公开(公告)号：US08983409B2
公开(公告)日：2015-03-17
申请号：US13172371
申请日：2011-06-29
申请人： Christopher Truong Ngo , Roman Zbigniew Arkiszewski , Brad Hunkele
发明人： Christopher Truong Ngo , Roman Zbigniew Arkiszewski , Brad Hunkele
IPC分类号： H01Q11/12 , H04B1/04 , H03F1/02 , H03F3/195 , H03F3/21 , H03F3/24 , H03F3/60 , H03F3/72
CPC分类号： H03F1/0227 , H03F1/0261 , H03F1/0277 , H03F3/195 , H03F3/211 , H03F3/245 , H03F3/602 , H03F3/72 , H03F2200/171 , H03F2200/222 , H03F2200/27 , H03F2200/318 , H03F2200/336 , H03F2200/387 , H03F2200/411 , H03F2200/414 , H03F2200/417 , H03F2200/451 , H03F2200/504 , H03F2200/534 , H03F2200/537 , H03F2200/541 , H03F2203/21106 , H03F2203/21142 , H03F2203/21157
摘要： An automatically configurable 2-wire/3-wire serial communications interface (AC23SCI), which includes start-of-sequence (SOS) detection circuitry and sequence processing circuitry, is disclosed. When the SOS detection circuitry is coupled to a 2-wire serial communications bus, the SOS detection circuitry detects an SOS of a received sequence based on a serial data signal and a serial clock signal. When the SOS detection circuitry is coupled to a 3-wire serial communications bus, the SOS detection circuitry detects the SOS of the received sequence based on a chip select (CS) signal. The SOS detection circuitry provides an indication of detection of the SOS to the sequence processing circuitry, which initiates processing of the received sequence using the serial data signal and the serial clock signal upon the detection of the SOS. As such, the AC23SCI automatically configures itself for operation with some 2-wire and some 3-wire serial communications buses without external intervention.
摘要翻译：公开了一种自动配置的2线/ 3线串行通信接口（AC23SCI），其包括序列启动（SOS）检测电路和序列处理电路。当SOS检测电路耦合到2线串行通信总线时，SOS检测电路基于串行数据信号和串行时钟信号检测接收序列的SOS。当SOS检测电路耦合到3线串行通信总线时，SOS检测电路基于芯片选择（CS）信号检测接收到的序列的SOS。 SOS检测电路提供对序列处理电路的SOS的检测的指示，该序列处理电路在检测到SOS时使用串行数据信号和串行时钟信号启动接收到的序列的处理。因此，AC23SCI自动配置自己的操作与一些2线和一些3线串行通信总线，无需外部干预。

5. 发明授权

US08624760B2 Apparatuses and methods for rate conversion and fractional delay calculation using a coefficient look up table 失效
$Apparatuses and methods for rate conversion and fractional delay calculation using a coefficient look up table$
标题翻译：使用系数查询表进行速率转换和分数延迟计算的装置和方法
公开(公告)号：US08624760B2
公开(公告)日：2014-01-07
申请号：US13423649
申请日：2012-03-19
申请人： Christopher Truong Ngo , Nadim Khlat
发明人： Christopher Truong Ngo , Nadim Khlat
IPC分类号： H03M7/00
CPC分类号： H03M7/3073 , H03M7/3082 , H04B17/13
摘要： A system and method for performing sample rate conversion and creating fractional delays to a signal is disclosed. The system comprises a filter, a look up table for storing coefficients for sample rate conversion and fractional delays, and control circuitry configured to use an indexing scheme to select one or more coefficients from the look up table for rate conversion and fractional delays. The coefficients stored in the look up table comprise the coefficients required to generate delays in desired increments of a sample rate. In the disclosed method, the one or more coefficients necessary for a desired sample rate and fractional delay are selected from a single look up table and provided to a filter to delay the signal based upon the input sample rate.
摘要翻译：公开了一种用于对信号进行采样率转换和产生分数延迟的系统和方法。该系统包括滤波器，用于存储用于采样率转换和分数延迟的系数的查找表以及配置为使用索引方案从查找表中选择一个或多个系数以用于速率转换和分数延迟的控制电路。存储在查找表中的系数包括以采样率的期望增量产生延迟所需的系数。在所公开的方法中，从单个查询表中选择所需采样率和分数延迟所需的一个或多个系数，并提供给滤波器以基于输入的采样率来延迟信号。

6. 发明授权

US07277497B2 System and method for transitioning between modulation formats in adjacent bursts triggering on data flow 有权
标题翻译：用于在相邻突发中的调制格式之间转换以触发数据流的系统和方法
公开(公告)号：US07277497B2
公开(公告)日：2007-10-02
申请号：US10985207
申请日：2004-11-10
申请人： Alexander Wayne Hietala , Christopher Truong Ngo
发明人： Alexander Wayne Hietala , Christopher Truong Ngo
IPC分类号： H03C5/00 , H04L25/49
CPC分类号： H04L27/2017 , H04L27/0008
摘要： A system and method are provided for transitioning between modulation formats in adjacent transmit bursts. The system includes a modulation system having a data interface, first modulation circuitry operating according to a first modulation format, and second modulation circuitry operating according to a second modulation format. During a transition between a first transmit burst in the first modulation format and a second transmit burst in the second modulation format, the data interface receives a timing signal signifying a start of data for the second transmit burst. In response to the timing signal, the second modulation circuitry resets, and the data interface delays the data for the second transmit burst by a modulator delay time. By delaying the data for the second transmit burst, a glitch caused by resetting the second modulation circuitry arrives at the output of the second modulation circuitry prior to the data for the second transmit burst.
摘要翻译：提供了一种用于在相邻发射脉冲串中的调制格式之间转换的系统和方法。该系统包括具有数据接口的调制系统，根据第一调制格式操作的第一调制电路和根据第二调制格式操作的第二调制电路。在第一调制格式的第一发送突发与第二调制格式的第二发送突发之间的转换期间，数据接口接收表示第二发送突发的数据开始的定时信号。响应于定时信号，第二调制电路复位，并且数据接口将第二发射脉冲串的数据延迟调制器延迟时间。通过延迟第二发送脉冲串的数据，由第二调制电路复位引起的毛刺在第二发射脉冲串的数据之前到达第二调制电路的输出端。

7. 发明授权

US06891414B1 Digital calibration for capacitor voltage non-linearity 有权
标题翻译：数字校准电容器电压非线性
公开(公告)号：US06891414B1
公开(公告)日：2005-05-10
申请号：US10794861
申请日：2004-03-05
申请人： Ryan Lee Bunch , Scott Robert Humphreys , Barry Travis Hunt, Jr. , Paul Gerard Martyniuk , Christopher Truong Ngo
发明人： Ryan Lee Bunch , Scott Robert Humphreys , Barry Travis Hunt, Jr. , Paul Gerard Martyniuk , Christopher Truong Ngo
IPC分类号： H03L7/06 , H03L7/089 , H03L7/093 , H03L7/18
CPC分类号： H03L7/0891 , H03L7/093 , H03L7/18
摘要： The present invention provides a system for adjusting a selectable capacitance of a variable capacitance array to compensate for voltage non-linearity of the variable capacitance array. In general, the system includes the variable capacitance array and a calibration circuit. The calibration circuit operates to determine a voltage across the variable capacitance array and to generate a capacitance selection signal based on the voltage across the variable capacitance array and a known capacitance versus voltage characteristic of the variable capacitance array.
摘要翻译：本发明提供了一种用于调整可变电容阵列的可选择电容以补偿可变电容阵列的电压非线性的系统。通常，该系统包括可变电容阵列和校准电路。校准电路用于确定可变电容阵列上的电压，并且基于可变电容阵列上的电压和可变电容阵列的已知电容对电压特性来产生电容选择信号。

8. 发明授权

US08983410B2 Configurable 2-wire/3-wire serial communications interface 有权
标题翻译：可配置2线/ 3线串行通信接口
公开(公告)号：US08983410B2
公开(公告)日：2015-03-17
申请号：US13289302
申请日：2011-11-04
申请人： William David Southcombe , Christopher Truong Ngo , David E. Jones , Chris Levesque , Scott Yoder , Terry J. Stockert
发明人： William David Southcombe , Christopher Truong Ngo , David E. Jones , Chris Levesque , Scott Yoder , Terry J. Stockert
IPC分类号： H01Q11/12 , H04B1/04 , G06F13/42
CPC分类号： G06F13/42 , G06F13/4291 , Y02D10/14 , Y02D10/151
摘要： A configurable 2-wire/3-wire serial communications interface (C23SCI), which includes start-of-sequence (SOS) detection circuitry and sequence processing circuitry, is disclosed. When the SOS detection circuitry is coupled to a 2-wire serial communications bus, the SOS detection circuitry detects an SOS of a received sequence based on a serial data signal and a serial clock signal. When the SOS detection circuitry is coupled to a 3-wire serial communications bus, the SOS detection circuitry detects the SOS of the received sequence based on a chip select (CS) signal. In response to detecting the SOS, the SOS detection circuitry provides an SOS detection signal to the sequence processing circuitry, which initiates processing of the received sequence using the serial data signal and the serial clock signal. The received sequence is associated with one of multiple serial communications protocols.
摘要翻译：公开了一种可配置的2线/ 3线串行通信接口（C23SCI），其包括序列启动（SOS）检测电路和序列处理电路。当SOS检测电路耦合到2线串行通信总线时，SOS检测电路基于串行数据信号和串行时钟信号检测接收序列的SOS。当SOS检测电路耦合到3线串行通信总线时，SOS检测电路基于芯片选择（CS）信号检测接收到的序列的SOS。响应于检测到SOS，SOS检测电路向序列处理电路提供SOS检测信号，其使用串行数据信号和串行时钟信号来启动接收到的序列的处理。所接收的序列与多个串行通信协议之一相关联。

9. 发明授权

US08933685B2 Protection system and method for DC-DC converters exposed to a strong magnetic field 有权
标题翻译：暴露于强磁场的DC-DC转换器的保护系统和方法
公开(公告)号：US08933685B2
公开(公告)日：2015-01-13
申请号：US13426947
申请日：2012-03-22
申请人： Mohammad Ahsanul Adeeb , John Endredy , Christopher Truong Ngo , Ashraf Rozek
发明人： Mohammad Ahsanul Adeeb , John Endredy , Christopher Truong Ngo , Ashraf Rozek
IPC分类号： H02M3/156 , H02M1/32 , H02M1/00
CPC分类号： H02M1/32 , H02M3/156 , H02M2001/0045
摘要： A protection system and method for protecting a direct current to direct current voltage converter (DC-DC converter) from a potentially damaging excessive output current due to exposure to a relatively strong magnetic field is disclosed. The system includes a detector circuit configured to monitor a signal characteristic of the DC-DC converter, and a linear regulator having an output coupled to the load output of the DC-DC converter. The system further includes a control system configured to disable a load output of the DC-DC converter and enable the output of the linear regulator when the detector detects that the signal characteristic has moved outside a predetermined threshold range. Moreover, the control system is further configured to disable the output of the linear regulator after a predetermined time period, and enable the load output of the DC-DC converter after the predetermined time period.
摘要翻译：公开了一种保护系统和方法，用于保护直流电流直流电压转换器（DC-DC转换器）免受由于暴露于较强磁场而导致的潜在损坏的过大输出电流。该系统包括被配置为监视DC-DC转换器的信号特性的检测器电路，以及具有耦合到DC-DC转换器的负载输出的输出的线性调节器。该系统还包括控制系统，该控制系统被配置为当检测器检测到信号特性已经超出预定阈值范围时，禁用DC-DC转换器的负载输出并使能线性调节器的输出。此外，控制系统进一步被配置为在预定时间段之后禁用线性调节器的输出，并且在预定时间段之后使能DC-DC转换器的负载输出。

10. 发明授权

US08667317B1 Circuitry including an RF front end circuit 有权
标题翻译：电路包括一个RF前端电路
公开(公告)号：US08667317B1
公开(公告)日：2014-03-04
申请号：US12884981
申请日：2010-09-17
申请人： Dharma Reddy Kadam , Nadim Khlat , Christopher Truong Ngo
发明人： Dharma Reddy Kadam , Nadim Khlat , Christopher Truong Ngo
IPC分类号： G06F1/04 , H04B1/38
CPC分类号： H04L7/04 , G06F13/385 , H04J3/0685
摘要： The present disclosure relates to RF front-end (RFFE) circuitry that includes multiple RFFE circuits, each of which may be provided by a separate integrated circuit (IC), front-end module, or both. As such, the RFFE circuits may be connected to one another using an RFFE serial communications bus. Further, one or more of the RFFE circuits may need an accurate clock source for analog-to-digital conversion (ADC), digital-to-analog conversion (DAC), calibration, sensor measurements, or the like. Instead of including an integral clock source circuit or receiving a separate external clock signal, an RFFE circuit may extract clock information from the RFFE serial communications bus to provide one or more clock signal. The clock information may be associated with one or more serial communications command via the RFFE serial communications bus.
摘要翻译：本公开涉及包括多个RFFE电路的RF前端（RFFE）电路，每个RFFE电路可以由单独的集成电路（IC），前端模块或两者提供。因此，RFFE电路可以使用RFFE串行通信总线彼此连接。此外，一个或多个RFFE电路可能需要用于模数转换（ADC），数模转换（DAC），校准，传感器测量等的精确时钟源。 RFFE电路不是包括集成时钟源电路或者接收单独的外部时钟信号，而是可以从RFFE串行通信总线提取时钟信息以提供一个或多个时钟信号。时钟信息可以经由RFFE串行通信总线与一个或多个串行通信命令相关联。

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