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1. 发明授权

US09026764B2 Memory system performing wear leveling based on deletion request 有权
标题翻译：基于删除请求执行磨损均衡的内存系统
公开(公告)号：US09026764B2
公开(公告)日：2015-05-05
申请号：US13420808
申请日：2012-03-15
申请人： Daisuke Hashimoto
发明人： Daisuke Hashimoto
IPC分类号： G06F12/00 , G06F12/02 , G06F12/10 , G06F13/00
CPC分类号： G06F12/0246 , G06F12/023 , G06F12/10 , G06F2212/7201 , G06F2212/7205 , G06F2212/7211
摘要： A memory system of a embodiments includes a first storing area having physical blocks and a second storing area recording a logical to physical translation table and an erasure count table keeping data erasure count in physical blocks. The memory system of the embodiments includes a controller which, when a logical address for deletion is notified, obtains data erasure count of a deletion physical block including a deletion area specified by the physical address corresponding to the logical address, and when a physical block having a small erasure count not more than a predetermined rate of the data erasure count exists in the erasure count table, reads out valid data for the memory system in the physical block having a small erasure count onto the second storing area, writes the above data into the deletion area, and invalidates the valid data in the physical block having a small erasure count.
摘要翻译：实施例的存储器系统包括具有物理块的第一存储区域和记录逻辑到物理转换表的第二存储区域和在物理块中保持数据擦除计数的擦除计数表。实施例的存储器系统包括控制器，当通知用于删除的逻辑地址时，获得包括由对应于逻辑地址的物理地址指定的删除区域的删除物理块的数据擦除计数，以及当具有在擦除计数表中存在不大于数据擦除计数的预定速率的小擦除次数，将具有小擦除次数的物理块中的存储器系统的有效数据读出到第二存储区域，将上述数据写入删除区域，使具有小擦除次数的物理块中的有效数据无效。

2. 发明申请

US20140147748A1 NEGATIVE ELECTRODE MATERIAL FOR LITHIUM SECONDARY BATTERY 审中-公开
标题翻译：用于锂二次电池的负极电极材料
公开(公告)号：US20140147748A1
公开(公告)日：2014-05-29
申请号：US13877976
申请日：2011-10-11
申请人： Koji Hisayuki , Daisuke Hashimoto
发明人： Koji Hisayuki , Daisuke Hashimoto
IPC分类号： H01M4/36
CPC分类号： H01M4/366 , C22C1/08 , H01M4/134 , H01M4/38 , H01M4/46 , H01M4/463 , H01M4/661 , H01M4/80 , H01M10/052 , H01M10/0585 , H01M2004/021
摘要： A lithium secondary battery negative electrode material 1 is in the form of a foil 2 or a plate, and includes a core layer 3 having electrical conductivity, and a porous layer 4 which is formed on at least one surface of the core layer 3, and which contains Al in an amount of 90 mass % or more. The porous layer 4 has a porosity of 30 to 70 vol. %. Pores 5 formed in the porous layer 4 have a pore size of 0.1 to 15 μm. The lithium secondary battery negative electrode material 1 realizes prolongation of the cycle life of a lithium secondary battery.
摘要翻译：锂二次电池负极材料1为箔2或板的形式，并且包括具有导电性的芯层3和形成在芯层3的至少一个表面上的多孔层4，以及其含有量为90质量％以上的Al。多孔层4的孔隙率为30〜70体积％。％。在多孔层4中形成的孔5的孔径为0.1〜15μm。锂二次电池负极材料1实现了锂二次电池的循环寿命的延长。

3. 发明申请

US20140113189A1 NEGATIVE ELECTRODE ACTIVE SUBSTANCE FOR LITHIUM SECONDARY BATTERY AND METHOD FOR PRODUCING SAME 有权
标题翻译：用于锂二次电池的负极电极活性物质及其生产方法
公开(公告)号：US20140113189A1
公开(公告)日：2014-04-24
申请号：US14110507
申请日：2011-10-11
申请人： Daisuke Hashimoto , Koji Hisayuki
发明人： Daisuke Hashimoto , Koji Hisayuki
IPC分类号： H01M4/46 , B02C23/06 , H01M4/36
CPC分类号： H01M4/463 , B02C23/06 , H01M4/134 , H01M4/1395 , H01M4/36 , H01M4/38 , H01M4/621 , H01M4/624 , H01M10/052 , Y02E60/122 , Y02P70/54
摘要： The present invention provides an anode material for a lithium secondary battery, which material realizes prolongation of the cycle life of a lithium secondary battery. The present invention relates to an anode active material for a lithium secondary battery, the active material containing a powder produced by a step of forming an etched foil through etching of both surfaces of a foil of Al having a purity of 90 mass % or higher, and a step of shredding the etched foil, the steps being carried out in this order.
摘要翻译：本发明提供了一种用于锂二次电池的负极材料，该材料实现了锂二次电池的循环寿命的延长。本发明涉及一种锂二次电池用负极活性物质，该活性物质含有通过蚀刻具有纯度为90质量％以上的Al的箔的两面来形成蚀刻箔的工序而制造的粉末，以及切割蚀刻的箔的步骤，该步骤以该顺序进行。

4. 发明申请

US20140000927A1 BUS-BAR SET AND MANUFACTURING METHOD THEREFOR 审中-公开
标题翻译：总线设置及其制造方法
公开(公告)号：US20140000927A1
公开(公告)日：2014-01-02
申请号：US13982614
申请日：2012-02-28
申请人： Daisuke Hashimoto , Kouji Fukumoto , Masaharu Suetani
发明人： Daisuke Hashimoto , Kouji Fukumoto , Masaharu Suetani
IPC分类号： H01B7/00 , H01B13/06
CPC分类号： H01B7/0018 , H01B13/06 , H01R11/288 , H01R43/24 , H02G5/005 , Y10T29/4922
摘要： The present invention is intended to provide a bus bar set that has excellent heat dissipation performance and mounting workability and prevents excessive heat generation due to an electrical connection failure, even when a cross section area of a conductive body is large. A bus bar set has a plurality of multilayer bus bars and an insulating member. The multilayer bus bars each include an intermediate portion having a plurality of layered plate-shaped conductive bodies and terminal portions having conductive bodies extending from two ends of the intermediate portion and connected to other members. The insulating member is composed of a flexible insulating body having a flat external shape, and covers and integrally connects the intermediate portions of the plurality of multilayer bus bars aligned in parallel with gaps therebetween on one plane.
摘要翻译：本发明旨在提供一种具有优异的散热性能和安装加工性的母线组，并且即使当导电体的横截面积大时也能防止由于电连接故障而导致的过热发生。母线组具有多个多层母线和绝缘构件。多层母线棒各自包括具有多个层叠的板状导电体的中间部分和具有从中间部分的两端延伸并连接到其它部件的导电体的端子部分。绝缘构件由具有平坦外形的柔性绝缘体构成，并且在一个平面上覆盖并整体地连接多个多层汇流条的中间部分与其间的间隙平行排列。

5. 发明申请

US20120284453A1 INFORMATION PROCESSING DEVICE, EXTERNAL STORAGE DEVICE, HOST DEVICE, RELAY DEVICE, CONTROL PROGRAM, AND CONTROL METHOD OF INFORMATION PROCESSING DEVICE 有权
标题翻译：信息处理装置，外部存储装置，主机装置，继电器装置，控制程序和信息处理装置的控制方法
公开(公告)号：US20120284453A1
公开(公告)日：2012-11-08
申请号：US13551060
申请日：2012-07-17
申请人： Daisuke HASHIMOTO
发明人： Daisuke HASHIMOTO
IPC分类号： G06F12/00
CPC分类号： G06F11/076 , G06F3/0605 , G06F3/0611 , G06F3/0616 , G06F3/0619 , G06F3/0632 , G06F3/0634 , G06F3/0653 , G06F3/0679 , G06F11/073 , G06F11/1458 , G06F12/0246 , G06F12/0804 , G06F12/0868 , G06F2201/805 , G06F2212/214 , G06F2212/7204 , G11C11/5621 , G11C16/0483
摘要： According to the embodiments, an external storage device switches to an interface controller for supporting only a read operation of nonvolatile memory when a shift condition for shifting to a read only mode is met. A host device switches to an interface driver for supporting only the read operation of the nonvolatile memory when determining to recognize as read only memory based on information acquired from the external storage device.
摘要翻译：根据实施例，当满足用于转换为只读模式的移位条件时，外部存储装置切换到仅支持非易失性存储器的读取操作的接口控制器。当基于从外部存储设备获取的信息确定为只读存储器时，主机设备切换到接口驱动器，以仅支持非易失性存储器的读取操作。

6. 发明申请

US20120246393A1 MEMORY SYSTEM AND CONTROL METHOD OF THE MEMORY SYSTEM 有权
标题翻译：存储系统的存储系统和控制方法
公开(公告)号：US20120246393A1
公开(公告)日：2012-09-27
申请号：US13420808
申请日：2012-03-15
申请人： Daisuke HASHIMOTO
发明人： Daisuke HASHIMOTO
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/023 , G06F12/10 , G06F2212/7201 , G06F2212/7205 , G06F2212/7211
摘要： A memory system of a embodiments includes a first storing area having physical blocks and a second storing area recording a logical to physical translation table and an erasure count table keeping data erasure count in physical blocks. The memory system of the embodiments includes a controller which, when a logical address for deletion is notified, obtains data erasure count of a deletion physical block including a deletion area specified by the physical address corresponding to the logical address, and when a physical block having a small erasure count not more than a predetermined rate of the data erasure count exists in the erasure count table, reads out valid data for the memory system in the physical block having a small erasure count onto the second storing area, writes the above data into the deletion area, and invalidates the valid data in the physical block having a small erasure count.
摘要翻译：实施例的存储器系统包括具有物理块的第一存储区域和记录逻辑到物理转换表的第二存储区域和在物理块中保持数据擦除计数的擦除计数表。实施例的存储器系统包括控制器，当通知用于删除的逻辑地址时，获得包括由对应于逻辑地址的物理地址指定的删除区域的删除物理块的数据擦除计数，以及当具有在擦除计数表中存在不大于数据擦除计数的预定速率的小擦除次数，将具有小擦除次数的物理块中的存储器系统的有效数据读出到第二存储区域，将上述数据写入删除区域，使具有小擦除次数的物理块中的有效数据无效。

7. 发明申请

US20120246388A1 MEMORY SYSTEM, NONVOLATILE STORAGE DEVICE, CONTROL METHOD, AND MEDIUM 有权
标题翻译：存储系统，非易失存储器件，控制方法和介质
公开(公告)号：US20120246388A1
公开(公告)日：2012-09-27
申请号：US13235394
申请日：2011-09-18
申请人： Daisuke HASHIMOTO
发明人： Daisuke HASHIMOTO
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F3/0614 , G06F3/0638 , G06F3/0679 , G06F2212/7209
摘要： According to one embodiment, a memory system includes a nonvolatile storage device and an information processing apparatus. The information processing apparatus includes a first control circuit configured to send a delete notification to the nonvolatile storage device to invalidate data in a first logical address area when read data corresponding to the first logical address area is the same as data expressed by a first function. The nonvolatile storage device include a nonvolatile storage medium, a management table configured to associate a logical address corresponding to valid data for the nonvolatile storage device with a physical address, and a second control circuit configured to update the management table to invalidate a logical address designated by the delete notification, and to send the data expressed by the first function to the information processing apparatus when a logical address included in a read instruction received from the information processing apparatus is invalid.
摘要翻译：根据一个实施例，存储器系统包括非易失性存储设备和信息处理设备。信息处理装置包括第一控制电路，被配置为当对应于第一逻辑地址区域的读取数据与由第一功能表示的数据相同时，向非易失性存储设备发送删除通知以使第一逻辑地址区域中的数据无效。非易失性存储装置包括非易失性存储介质，管理表，被配置为将与非易失性存储装置的有效数据相对应的逻辑地址与物理地址相关联;以及第二控制电路，被配置为更新管理表以使指定的逻辑地址无效并且当从信息处理设备接收的读取指令中包括的逻辑地址无效时，将由第一功能表示的数据发送到信息处理设备。

8. 发明申请

US20120144097A1 MEMORY SYSTEM AND DATA DELETING METHOD 有权
标题翻译：记忆系统和数据删除方法
公开(公告)号：US20120144097A1
公开(公告)日：2012-06-07
申请号：US13312129
申请日：2011-12-06
申请人： Daisuke HASHIMOTO
发明人： Daisuke HASHIMOTO
IPC分类号： G06F12/16
CPC分类号： G06F12/0246 , G06F3/0608 , G06F3/061 , G06F3/0652 , G06F3/0679 , G06F12/08 , G06F2212/7205
摘要： According to one embodiment, a memory system includes: a memory area; a transfer processing unit that stores write data received from a host apparatus in the memory area; a delete notification buffer that accumulates a delete notification; and a delete notification processing unit. The delete notification processing unit collectively reads out a plurality of delete notifications from the delete notification buffer and classifies the read-out delete notifications for each unit area. The delete notification processing unit sequentially executes, for each unit area, processing for collectively invalidating write data related to one or more delete notifications classified in a same unit area and, in executing processing for one unit area in the processing sequentially executed for the each unit area, invalidates all write data stored in the one unit area after copying write data excluding write data to be invalidated stored in the one unit area to another unit area.
摘要翻译：根据一个实施例，存储器系统包括：存储区域; 传送处理单元，其将从主机装置接收的写入数据存储在存储区域中; 删除通知缓冲器，累积删除通知; 和删除通知处理单元。删除通知处理单元从删除通知缓冲器中共同读出多个删除通知，并对每个单位区域的读出删除通知进行分类。删除通知处理单元对于每个单位区域顺序地执行用于共同使与分类在同一单位区域中的一个或多个删除通知相关的写入数据无效的处理，并且在对于每个单元顺序执行的处理中对一个单位区域执行处理区域，在将除了存储在一个单位区域中的无效的写入数据的写入数据复制到另一单位区域之后，使存储在一个单位区域中的所有写入数据无效。

9. 发明申请

US20110175928A1 Map Display Device and Map Display Method 审中-公开
标题翻译：地图显示设备和地图显示方式
公开(公告)号：US20110175928A1
公开(公告)日：2011-07-21
申请号：US12912149
申请日：2010-10-26
申请人： Daisuke HASHIMOTO
发明人： Daisuke HASHIMOTO
IPC分类号： G09G5/00
CPC分类号： G09G5/00 , G01C21/3682 , G06F3/0485 , G06F3/0488 , G06F2203/04804 , G09G2340/10 , G09G2340/14
摘要： A map display device, including a map display control unit that causes a map to be displayed on a display monitor and causes a facility icon to be displayed being superimposed on a map; an indication unit that indicates a portion of an area of a map displayed on the display monitor; a specification unit that specifies a facility icon existing in an indicated area indicated by the indication unit from among facility icons displayed on the display monitor; and a changer that changes a display mode of a specified facility icon specified by the specification unit into a display mode in which a visibility of image information on a map is not disturbed.
摘要翻译：一种地图显示装置，包括地图显示控制单元，其使得将地图显示在显示监视器上并使得将设施图标显示在地图上; 指示单元，其指示显示在显示监视器上的地图的一部分区域; 指定单元，其从显示在显示监视器上的设施图标中指定存在于由指示单元指示的指示区域中的设施图标; 以及更改器，其将指定单元指定的指定设施图标的显示模式改变为不扰乱地图上的图像信息的可视性的显示模式。

10. 发明申请

US20110063886A1 SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD OF THE SAME 失效
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：US20110063886A1
公开(公告)日：2011-03-17
申请号：US12703548
申请日：2010-02-10
申请人： Daisuke HASHIMOTO , Daisaburo TAKASHIMA
发明人： Daisuke HASHIMOTO , Daisaburo TAKASHIMA
IPC分类号： G11C11/22 , G11C29/00 , G11C17/18
CPC分类号： G11C29/24 , G11C11/22 , G11C17/143 , G11C29/785
摘要： A memory includes a cell region; a spare region including a spare block; a fuse region storing remedy information necessary for an access to the spare block instead of a remedy target block, the fuse region comprising non-defective cells in the remedy target block, or including cells in a first block of the spare region; an initial reading fuse storing a block address for identifying the remedy target block or the first block allocated as the fuse region, and a selection address for selecting a region in the remedy target block or a region in the first block allocated as the fuse region; and a controller configured to acquire the remedy information from the fuse region based on the block address and the selection address, and to change the access to the remedy target block to the access to the spare block based on the remedy information.
摘要翻译：存储器包括单元区域; 包括备用区的备用区; 熔丝区域，其存储访问所述备用块而不是补救目标块所需的补救信息，所述熔丝区域包括所述补救目标块中的无缺陷单元，或者包括所述备用区域的第一块中的单元; 存储用于识别补救目标块的块地址的初始读取熔丝或分配为熔丝区的第一块的初始读取熔丝，以及用于选择补救目标块中的区域或分配为熔丝区域的第一块中的区域的选择地址; 以及控制器，被配置为基于所述块地址和所述选择地址从所述保险丝区域获取补救信息，并且基于所述补救信息来将对所述补救目标块的访问改变为对所述备用块的访问。

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