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1. 发明授权

US09185406B2 Image decoding device, image coding device, methods thereof, programs thereof, integrated circuits thereof, and transcoding device 有权
标题翻译：图像解码装置，图像编码装置，其方法，程序，集成电路和代码转换装置
公开(公告)号：US09185406B2
公开(公告)日：2015-11-10
申请号：US13496341
申请日：2011-09-09
申请人： Takeshi Tanaka , Naoki Yoshimatsu , Keiichi Kurokawa , Daisuke Iwahashi
发明人： Takeshi Tanaka , Naoki Yoshimatsu , Keiichi Kurokawa , Daisuke Iwahashi
IPC分类号： H04N11/02 , H04N11/04 , H04N19/436 , H04N19/50 , H04N19/593 , H04N19/16 , H04N19/44 , H04N19/82 , H04N19/40
CPC分类号： H04N19/436 , H04N19/16 , H04N19/40 , H04N19/44 , H04N19/50 , H04N19/593 , H04N19/82
摘要： An image decoding device for increasing decoding efficiency and reducing the number of memory accesses includes a division unit dividing a picture into first and second coded image data; and first and second decoding units decoding, in parallel, the first and second coded image data and storing decoding results into a frame storage unit. The first and second decoding units decode the first and second coded image data using second and first decoding result information, respectively, and store the resulting first and second decoding result information into an information storage unit. When decoding a target macroblock, each of the first and second decoding units performs image processing on the corresponding second or first decoding result information indicating part of the decoded macroblock included in the macroblock line adjacent to the macroblock line including the target macroblock, and the target macroblock.
摘要翻译：一种用于提高解码效率并减少存储器访问次数的图像解码装置包括将图像分割为第一和第二编码图像数据的分割单元; 并且第一和第二解码单元并行地解码第一和第二编码图像数据，并将解码结果存储到帧存储单元中。第一和第二解码单元分别使用第二和第一解码结果信息解码第一和第二编码图像数据，并将得到的第一和第二解码结果信息存储到信息存储单元中。当解码目标宏块时，第一和第二解码单元中的每一个对与包括目标宏块的宏块行相邻的宏块行中包括的解码宏块的对应的第二或第一解码结果信息执行图像处理，并且目标宏块。

2. 发明授权

US08982964B2 Image decoding device, image coding device, methods thereof, programs thereof, integrated circuits thereof, and transcoding device 有权
标题翻译：图像解码装置，图像编码装置，其方法，程序，集成电路和代码转换装置
公开(公告)号：US08982964B2
公开(公告)日：2015-03-17
申请号：US13575033
申请日：2011-09-09
申请人： Takeshi Tanaka , Naoki Yoshimatsu , Keiichi Kurokawa , Daisuke Iwahashi
发明人： Takeshi Tanaka , Naoki Yoshimatsu , Keiichi Kurokawa , Daisuke Iwahashi
IPC分类号： H04N7/12 , H04N19/436 , H04N19/16 , H04N19/44 , H04N19/40 , H04N19/50 , H04N19/593 , H04N19/82
CPC分类号： H04N19/436 , H04N19/16 , H04N19/40 , H04N19/44 , H04N19/50 , H04N19/593 , H04N19/82
摘要： An image decoding device which increases decoding efficiency and can be easily implemented includes: a division unit dividing coded image data into first and second coded image data; a frame storage unit; first and second decoding units decoding, in parallel, the first and second coded image data; and an information storage unit. The first decoding unit decodes the first coded image data using second decoding result information stored in the information storage unit and stores, as first decoding result information, a part of information generated by the decoding into the information storage unit. The second decoding unit decodes the second coded image data using the first decoding result information stored in the information storage unit and stores, as the second decoding result information, a part of information generated by the decoding into the information storage unit.
摘要翻译：提高解码效率并且可以容易地实现的图像解码装置包括：分割单元，将编码图像数据分割成第一和第二编码图像数据; 一个帧存储单元; 第一和第二解码单元并行地解码第一和第二编码图像数据; 和信息存储单元。第一解码单元使用存储在信息存储单元中的第二解码结果信息对第一编码图像数据进行解码，并将由解码生成的信息的一部分作为第一解码结果信息存储到信息存储单元中。第二解码单元使用存储在信息存储单元中的第一解码结果信息对第二编码图像数据进行解码，并将通过解码生成的信息的一部分存储到信息存储单元中作为第二解码结果信息。

3. 发明申请

US20100254620A1 IMAGE DECODING APPARATUS AND IMAGE DECODING METHOD 审中-公开
标题翻译：图像解码设备和图像解码方法
公开(公告)号：US20100254620A1
公开(公告)日：2010-10-07
申请号：US12746859
申请日：2009-10-09
申请人： Daisuke Iwahashi , Naoki Yoshimatsu , Takeshi Tanaka
发明人： Daisuke Iwahashi , Naoki Yoshimatsu , Takeshi Tanaka
IPC分类号： G06K9/46
CPC分类号： H04N19/573 , H04N19/174 , H04N19/436 , H04N19/44 , H04N19/61 , H04N19/70
摘要： To provide a simply-structured image decoding apparatus which appropriately executes parallel decoding processing.The image decoding apparatus includes: a stream segmentation unit (130) which generates four segment streams by segmenting each of the pictures included in a bit stream into plural MB lines, and assigning each of the plural MB lines to a corresponding one of the four segment streams to be generated; and four decoding engines (120) which decode the respective four segment streams in parallel. When the stream segmentation unit (130) segments a slice in the picture into slice portions and assigns the respective slice portions to plural segment streams, the stream segmentation unit (130) reconstructs, as a new slice, the slice portion group including at least one slice portion to be assigned to a corresponding one of the segment streams so that the slice portion group is recognized as a slice by the associated one of the decoding engines (120).
摘要翻译：提供一种适当执行并行解码处理的简单结构的图像解码装置。图像解码装置包括：流分割单元，其通过将包含在比特流中的每个图像分割成多个MB线来生成四个分段流，并且将多个MB线中的每一个分配给四个分段中的相应一个要生成的流; 以及四个解码引擎（120），它们并行地解码相应的四个段流。当流分割单元（130）将图像中的切片分割成切片部分并将各个切片部分分配给多个分段流时，流分割单元（130）将包括至少一个切片部分被分配给相应的一个分段流，使得切片部分组被解码引擎（120）中的相关联的一个识别为切片。

4. 发明申请

US20100017548A1 BUFFER MANAGEMENT DEVICE, BUFFER MANAGEMENT METHOD, AND INTEGRATED CIRCUIT FOR BUFFER MANAGEMENT 有权
标题翻译：缓冲区管理设备，缓冲区管理方法和缓存管理集成电路
公开(公告)号：US20100017548A1
公开(公告)日：2010-01-21
申请号：US12523099
申请日：2008-11-27
申请人： Daisuke Iwahashi , Hideyuki Kanzaki
发明人： Daisuke Iwahashi , Hideyuki Kanzaki
IPC分类号： G06F5/08 , G06F3/00
CPC分类号： H04N21/44004 , H04L49/90 , H04N21/23406 , H04N21/8456
摘要： A buffer management apparatus that sequentially receives L (L>1) types of data and transmits the L types of data to an external device, including: a reception unit that receives data; M (M
摘要翻译：一种缓冲器管理装置，其顺序地接收L（L> 1）类型的数据并将L类型的数据发送到外部设备，包括：接收数据的接收单元; M（M

5. 发明申请

US20140006665A1 RESOURCE REQUEST ARBITRATION DEVICE, RESOURCE REQUEST ARBITRATION SYSTEM, RESOURCE REQUEST ARBITRATION METHOD, INTEGRATED CIRCUIT, AND PROGRAM 有权
标题翻译：资源请求仲裁设备，资源请求仲裁系统，资源请求仲裁方法，集成电路和程序
公开(公告)号：US20140006665A1
公开(公告)日：2014-01-02
申请号：US13821392
申请日：2012-07-27
申请人： Hiroshi Amano , Daisuke Iwahashi
发明人： Hiroshi Amano , Daisuke Iwahashi
IPC分类号： G06F13/362
CPC分类号： G06F13/362
摘要： A resource request arbitration device is connected with each of a plurality of masters, and arbitrates transfer requests issued by the masters. The resource request arbitration device includes a plurality of counters each indicating a slack time of a transfer request issued by a master corresponding to the counter, and compares counter values stored in the counters by a tournament method, and specifies a master that has issued a transfer request having the highest priority. The resource request arbitration device grants access permission to the specified master to permit the specified master to use a slave.
摘要翻译：资源请求仲裁装置与多个主机中的每一个连接，并且仲裁由主机发出的转移请求。资源请求仲裁装置包括多个计数器，每个计数器指示由与计数器相对应的主机发出的转移请求的松弛时间，并且通过比赛方法比较存储在计数器中的计数器值，并指定已经发送转移的主控请求具有最高优先级。资源请求仲裁设备授予对指定主机的访问许可，以允许指定的主机使用从站。

6. 发明授权

US08438523B2 Integrated circuit manufacturing method and semiconductor integrated circuit 有权
标题翻译：集成电路制造方法和半导体集成电路
公开(公告)号：US08438523B2
公开(公告)日：2013-05-07
申请号：US13383335
申请日：2011-05-27
申请人： Daisuke Iwahashi , Masayoshi Tojima , Tokuzo Kiyohara
发明人： Daisuke Iwahashi , Masayoshi Tojima , Tokuzo Kiyohara
IPC分类号： G06F17/50
CPC分类号： H01L27/0207
摘要： In layout design step of the semiconductor integrated circuit manufacturing method, when it is found that the wiring length between an external terminal and an IO block (external terminal I/F circuit) corresponding to the external terminal increases after a floorplan of a circuit including a functional block and the IO block is determined, placement of the IO block is determined such that the IO block is placed close to the external terminal to alleviate constraints on the wiring between the IO block and the external terminal, and timing adjustment circuits whose number is determined according to the wiring length of a bus (or a shared bus) connecting a data transfer circuit and the IO block is inserted into the bus.
摘要翻译：在半导体集成电路制造方法的布局设计步骤中，当发现在外部端子与外部端子对应的IO块（外部端子I / F电路）之间的布线长度在包括功能块和IO块被确定，IO块的放置被确定为使得IO块靠近外部端子放置以减轻对IO块和外部端子之间的布线的约束，以及定时调整电路的数量是根据将数据传输电路和IO块连接的总线（或共享总线）的布线长度确定为总线。

7. 发明申请

US20120275516A1 IMAGE DECODING DEVICE, IMAGE CODING DEVICE, METHODS THEREOF, PROGRAMS THEREOF, INTEGRATED CIRCUITS THEREOF, AND TRANSCODING DEVICE 有权
标题翻译：图像解码装置，图像编码装置，其方法，其程序，其集成电路和转换装置
公开(公告)号：US20120275516A1
公开(公告)日：2012-11-01
申请号：US13496341
申请日：2011-09-09
申请人： Takeshi Tanaka , Naoki Yoshimatsu , Keiichi Kurokawa , Daisuke Iwahashi
发明人： Takeshi Tanaka , Naoki Yoshimatsu , Keiichi Kurokawa , Daisuke Iwahashi
IPC分类号： H04N7/32
CPC分类号： H04N19/436 , H04N19/16 , H04N19/40 , H04N19/44 , H04N19/50 , H04N19/593 , H04N19/82
摘要： An image decoding device (C100) for increasing decoding efficiency and reducing the number of memory accesses includes: a division unit (C101) dividing a picture into first and second coded image data; and first and second decoding units (C103 and C104) decoding, in parallel, the first and second coded image data and storing decoding results into a frame storage unit (C102). The first and second decoding units (C103 and C104) decode the first and second coded image data using second and first decoding result information, respectively, and store the resulting first and second decoding result information into an information storage unit (C105). When decoding a target macroblock, each of the first and second decoding units performs image processing on: the corresponding second or first decoding result information indicating part of the decoded macroblock included in the macroblock line adjacent to the macroblock line including the target macroblock; and the target macroblock.
摘要翻译：一种用于提高解码效率并减少存储器访问次数的图像解码装置（C100）包括：将图像分割为第一和第二编码图像数据的分割单元（C101）并且第一和第二解码单元（C103和C104）并行地解码第一和第二编码图像数据，并将解码结果存储到帧存储单元（C102）中。第一和第二解码单元（C103和C104）分别使用第二和第一解码结果信息解码第一和第二编码图像数据，并将得到的第一和第二解码结果信息存储到信息存储单元（C105）中。当解码目标宏块时，第一和第二解码单元中的每一个对与包括目标宏块的宏块行相邻的宏块行中包含的解码宏块的部分的相应的第二或第一解码结果信息执行图像处理; 和目标宏块。

8. 发明授权

US07962674B2 Buffer management device, buffer management method, and integrated circuit for buffer management 有权
标题翻译：缓冲管理装置，缓冲管理方法和缓冲管理集成电路
公开(公告)号：US07962674B2
公开(公告)日：2011-06-14
申请号：US12523099
申请日：2008-11-27
申请人： Daisuke Iwahashi , Hideyuki Kanzaki
发明人： Daisuke Iwahashi , Hideyuki Kanzaki
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： H04N21/44004 , H04L49/90 , H04N21/23406 , H04N21/8456
摘要： A buffer management apparatus that sequentially receives L (L>1) types of data and transmits the L types of data to an external device, including: a reception unit that receives data; M (M
摘要翻译：一种缓冲器管理装置，其顺序地接收L（L> 1）类型的数据并将L类型的数据发送到外部设备，包括：接收数据的接收单元; M（M

9. 发明申请

US20100322317A1 IMAGE DECODING APPARATUS AND IMAGE DECODING METHOD 审中-公开
标题翻译：图像解码设备和图像解码方法
公开(公告)号：US20100322317A1
公开(公告)日：2010-12-23
申请号：US12866430
申请日：2009-10-27
申请人： Naoki Yoshimatsu , Daisuke Iwahashi , Takeshi Tanaka
发明人： Naoki Yoshimatsu , Daisuke Iwahashi , Takeshi Tanaka
IPC分类号： H04N7/26
CPC分类号： H04N19/40 , H04N19/174 , H04N19/436 , H04N19/44 , H04N19/70
摘要： To provide a simply-structured image decoding apparatus which appropriately executes parallel decoding processing. The image decoding apparatus includes: a stream segmentation unit (130) which generates plural segment streams by segmenting each of the pictures included in a bit stream into plural MB lines, and assigning each of the plural MB lines to a corresponding one of the plural segment streams to be generated; and plural decoding engines (120) which decode the respective plural segment streams in parallel. In the case where at least two consecutive MB lines in the bit stream have a dependency indicated by a predetermined code word, the stream segmentation unit (130) sets the code word to the segment streams so as to update the dependencies to new dependencies depending on the contexts of MB lines in the respective segment streams.
摘要翻译：提供一种适当执行并行解码处理的简单结构的图像解码装置。图像解码装置包括：流分割单元，通过将包含在比特流中的每个图像分割成多个MB线来生成多个分段流，并将多个MB线分配给多个分段中的相应一个要生成的流; 以及并行解码各个分段流的多个解码引擎（120）。在比特流中至少两个连续的MB线具有由预定码字指示的依赖性的情况下，流分段单元（130）将码字设置为片段流，以便根据依赖关系将依赖性更新为新依赖各行段流中MB行的上下文。

10. 发明授权

US09367498B2 Resource request arbitration device, resource request arbitration system, resource request arbitration method, integrated circuit, and program 有权
标题翻译：资源请求仲裁设备，资源请求仲裁系统，资源请求仲裁方法，集成电路和程序
公开(公告)号：US09367498B2
公开(公告)日：2016-06-14
申请号：US13821392
申请日：2012-07-27
申请人： Hiroshi Amano , Daisuke Iwahashi
发明人： Hiroshi Amano , Daisuke Iwahashi
IPC分类号： G06F13/36 , G06F13/362
CPC分类号： G06F13/362
摘要： A resource request arbitration device is connected with each of a plurality of masters, and arbitrates transfer requests issued by the masters. The resource request arbitration device includes a plurality of counters each indicating a slack time of a transfer request issued by a master corresponding to the counter, and compares counter values stored in the counters by a tournament method, and specifies a master that has issued a transfer request having the highest priority. The resource request arbitration device grants access permission to the specified master to permit the specified master to use a slave.
摘要翻译：资源请求仲裁装置与多个主机中的每一个连接，并且仲裁由主机发出的转移请求。资源请求仲裁装置包括多个计数器，每个计数器指示由与计数器相对应的主机发出的转移请求的松弛时间，并且通过比赛方法比较存储在计数器中的计数器值，并指定已经发送转移的主控请求具有最高优先级。资源请求仲裁设备授予对指定主机的访问许可，以允许指定的主机使用从站。

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