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    • 6. 发明授权
    • Input/output cache with mapped pages allocated for caching direct
(virtual) memory access input/output data based on type of I/O devices
    • 输入/输出缓存具有分配用于缓存直接(虚拟)存储器访问基于I / O设备类型的输入/输出数据的映射页面
    • US5263142A
    • 1993-11-16
    • US999193
    • 1992-12-28
    • John WatkinsDavid LabudaWilliam C. Van Loo
    • John WatkinsDavid LabudaWilliam C. Van Loo
    • G06F12/08G06F13/28G06F13/00
    • G06F12/0875G06F13/28
    • An I/O cache is provided to a computer system comprising a main memory and a number of DVMA/DMA I/O devices for caching I/O data between the main memory and the DVMA/DMA I/O devices. The I/O cache selectively caches the I/O data in accordance to the device class types of the DVMA/DMA devices. The I/O cache comprises an I/O cache data array, an I/O cache address tag array, an I/O cache mapper, and I/O cache control logic. The I/O cache data array comprises a number I/O cache lines, each having a number of I/O cache blocks, for storing I/O data between the main memory and the DVMA/DMA devices. The I/O cache tag comprises a number of corresponding I/O cache address tag entries, each having a number of I/O cache address tags and associated control information, for storing address and control information for the I/O data stored in the I/O cache lines. The I/O cache mapper maps the dynamically or statically allocated I/O buffers in main memory of each DVMA/DMA device having a cacheable device class type to a set of dynamically or statically assigned unique I/O cache buffers in the I/O cache data array, thereby ensuring that no two DVMA/DMA devices with cacheable I/O data will share the same I/O cache block. The I/O control logic controls accesses, indexes and updates to the I/O cache mapper, the I/O cache tag and data arrays.
    • 将I / O缓存提供给包括主存储器和多个DVMA / DMA I / O设备的计算机系统,用于在主存储器和DVMA / DMA I / O设备之间缓存I / O数据。 I / O缓存根据DVMA / DMA设备的设备类型选择性地缓存I / O数据。 I / O缓存包括I / O高速缓存数据阵列,I / O高速缓存地址标签阵列,I / O高速缓存映射器和I / O高速缓存控制逻辑。 I / O缓存数据阵列包括数字I / O高速缓存线,每条I / O高速缓存线都具有多个I / O高速缓存块,用于在主存储器和DVMA / DMA设备之间存储I / O数据。 I / O缓存标签包括多个对应的I / O高速缓存地址标签条目,每个具有多个I / O高速缓存地址标签和相关联的控制信息,用于存储存储在I / O缓存中的I / O数据的地址和控制信息 I / O缓存行。 I / O缓存映射器将具有可缓存设备类类型的每个DVMA / DMA设备的主存储器中的动态或静态分配的I / O缓冲器映射到I / O中的一组动态或静态分配的唯一I / O高速缓存缓冲区 缓存数据阵列,从而确保没有具有可缓存I / O数据的两个DVMA / DMA设备将共享相同的I / O高速缓存块。 I / O控制逻辑控制对I / O缓存映射器,I / O缓存标签和数据阵列的访问,索引和更新。
    • 7. 发明授权
    • Maintaining data coherency between a central cache, an I/O cache and a
memory
    • 维护中央缓存,I / O缓存和内存之间的数据一致性
    • US5247648A
    • 1993-09-21
    • US879162
    • 1992-04-30
    • John WatkinsDavid LabudaWilliam C. Van Loo
    • John WatkinsDavid LabudaWilliam C. Van Loo
    • G06F12/08
    • G06F12/0835G06F12/0866G06F12/0897G06F12/0815G06F2212/303
    • An I/O write back cache memory and a data coherency method is provided to a computer system having a cache and a main memory. The data coherency method includes partitioning the main memory into memory segments, dynamically assigning and reassigning the ownership of the memory segments either to the cache memory or the I/O write back cache memory. The ownership of the memory segments controls the accessibility and cacheability of the memory segments for read and write cycles performed by the CPU and I/O devices. During reassignment, various data management actions are taken to ensure data coherency. As a result, the I/O devices can perform read and write cycles addressed against the cache and main memory in a manner that increases system performance with minimal increase in hardware and complexity cost.
    • 将I / O回写高速缓冲存储器和数据一致性方法提供给具有高速缓存和主存储器的计算机系统。 数据一致性方法包括将主存储器划分为存储器段,动态分配和重新分配存储器段的所有权到高速缓冲存储器或I / O回写高速缓冲存储器。 存储器段的所有权控制由CPU和I / O设备执行的读取和写入周期的存储器段的可访问性和可缓存性。 在重新分配时,采取各种数据管理措施来确保数据一致性。 因此,I / O设备可以以降低硬件和复杂性成本的增加来提高系统性能的方式执行针对高速缓存和主存储器的读写周期。
    • 8. 发明授权
    • System with multiple conditional commit databases
    • 具有多个条件提交数据库的系统
    • US08572056B2
    • 2013-10-29
    • US13548074
    • 2012-07-12
    • David LabudaKeith Brefczynski
    • David LabudaKeith Brefczynski
    • G06F17/30
    • H04W4/023G06F17/30362G06F17/30371H04B17/318H04W4/06H04W4/80H04W52/0216Y02D70/142Y02D70/144
    • A system for processing a transaction is disclosed. The system comprises a processor and a memory. The processor is configured to check a condition using data in a first database, wherein the data is associated with a transaction, wherein the data in the first database is latched before checking the condition and is unlatched after checking the condition. The processor is further configured to indicate to a second database to check the condition using data in the second database, wherein the data is associated with the transaction. The data in the second database is latched before checking the condition and is unlatched after checking the condition. The memory is coupled to the processor and configured to provide the processor with instructions.
    • 公开了一种用于处理交易的系统。 该系统包括处理器和存储器。 处理器被配置为使用第一数据库中的数据来检查条件,其中数据与事务相关联,其中第一数据库中的数据在检查条件之前被锁存,并且在检查条件之后被解锁。 处理器还被配置为向第二数据库指示使用第二数据库中的数据来检查条件,其中数据与事务相关联。 在检查条件之前,第二个数据库中的数据被锁存,并在检查条件后解锁。 存储器耦合到处理器并且被配置为向处理器提供指令。