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1. 发明授权

US08913967B2 Feedback based buck timing of a direct current (DC)-DC converter 有权
标题翻译：直流（DC）-DC转换器的基于反馈的降压时序
公开(公告)号：US08913967B2
公开(公告)日：2014-12-16
申请号：US13287726
申请日：2011-11-02
申请人： David Zimlich , Jean-Christophe Berchtold , Joseph Hubert Colles , David E. Jones , Chris Levesque , William David Southcombe , Scott Yoder , Terry J. Stockert
发明人： David Zimlich , Jean-Christophe Berchtold , Joseph Hubert Colles , David E. Jones , Chris Levesque , William David Southcombe , Scott Yoder , Terry J. Stockert
IPC分类号： H01Q11/12 , H04B1/04 , H04B1/38 , H03F3/21 , H03F1/02 , H03F3/72 , H03F3/24 , H03F3/195 , H03F3/60
CPC分类号： H03F1/0227 , H03F1/0261 , H03F1/0277 , H03F3/195 , H03F3/211 , H03F3/245 , H03F3/602 , H03F3/72 , H03F2200/171 , H03F2200/222 , H03F2200/27 , H03F2200/318 , H03F2200/336 , H03F2200/387 , H03F2200/411 , H03F2200/414 , H03F2200/417 , H03F2200/451 , H03F2200/504 , H03F2200/534 , H03F2200/537 , H03F2200/541 , H03F2203/21106 , H03F2203/21142 , H03F2203/21157
摘要： At least a first shunt switching element and switching control circuitry of a first switching power supply are disclosed. At least the first shunt switching element is coupled between a ground and an output inductance node of the first switching power supply. The first switching power supply provides a buck output signal from the output inductance node. The switching control circuitry selects one of an ON state and an OFF state of the first shunt switching element. When the buck output signal is above a first threshold, the switching control circuitry is inhibited from selecting the ON state. The first switching power supply provides a first switching power supply output signal based on the buck output signal. By using feedback based on the buck output signal, the switching control circuitry may refine the timing of switching between series switching elements and shunt switching elements to increase efficiency.
摘要翻译：公开了至少第一分流开关元件和第一开关电源的开关控制电路。至少第一分流开关元件耦合在第一开关电源的接地和输出电感节点之间。第一开关电源从输出电感节点提供降压输出信号。开关控制电路选择第一分路开关元件的接通状态和断开状态之一。当降压输出信号高于第一阈值时，禁止开关控制电路选择接通状态。第一开关电源基于降压输出信号提供第一开关电源输出信号。通过使用基于降压输出信号的反馈，开关控制电路可以细化在串联开关元件和分流开关元件之间切换的时序，以提高效率。

2. 发明申请

US20120280747A1 FEEDBACK BASED BUCK TIMING OF A DIRECT CURRENT (DC)-DC CONVERTER 有权
标题翻译：直流电流（DC）-DC转换器的基于反馈的BUCK时序
公开(公告)号：US20120280747A1
公开(公告)日：2012-11-08
申请号：US13287726
申请日：2011-11-02
申请人： David Zimlich , Jean-Christophe Berchtold , Joseph Hubert Colles , David E. Jones , Chris Levesque , William David Southcombe , Scott Yoder , Terry J. Stockert
发明人： David Zimlich , Jean-Christophe Berchtold , Joseph Hubert Colles , David E. Jones , Chris Levesque , William David Southcombe , Scott Yoder , Terry J. Stockert
IPC分类号： H03F3/68 , G05F3/08
CPC分类号： H03F1/0227 , H03F1/0261 , H03F1/0277 , H03F3/195 , H03F3/211 , H03F3/245 , H03F3/602 , H03F3/72 , H03F2200/171 , H03F2200/222 , H03F2200/27 , H03F2200/318 , H03F2200/336 , H03F2200/387 , H03F2200/411 , H03F2200/414 , H03F2200/417 , H03F2200/451 , H03F2200/504 , H03F2200/534 , H03F2200/537 , H03F2200/541 , H03F2203/21106 , H03F2203/21142 , H03F2203/21157
摘要： At least a first shunt switching element and switching control circuitry of a first switching power supply are disclosed. At least the first shunt switching element is coupled between a ground and an output inductance node of the first switching power supply. The first switching power supply provides a buck output signal from the output inductance node. The switching control circuitry selects one of an ON state and an OFF state of the first shunt switching element. When the buck output signal is above a first threshold, the switching control circuitry is inhibited from selecting the ON state. The first switching power supply provides a first switching power supply output signal based on the buck output signal. By using feedback based on the buck output signal, the switching control circuitry may refine the timing of switching between series switching elements and shunt switching elements to increase efficiency.
摘要翻译：公开了至少第一分流开关元件和第一开关电源的开关控制电路。至少第一分流开关元件耦合在第一开关电源的接地和输出电感节点之间。第一开关电源从输出电感节点提供降压输出信号。开关控制电路选择第一分路开关元件的接通状态和断开状态之一。当降压输出信号高于第一阈值时，禁止开关控制电路选择接通状态。第一开关电源基于降压输出信号提供第一开关电源输出信号。通过使用基于降压输出信号的反馈，开关控制电路可以细化在串联开关元件和分流开关元件之间切换的时序，以提高效率。

3. 发明申请

US20120280746A1 DC-DC CONVERTER SEMICONDUCTOR DIE STRUCTURE 有权
标题翻译： DC-DC转换器半导体结构
公开(公告)号：US20120280746A1
公开(公告)日：2012-11-08
申请号：US13287713
申请日：2011-11-02
申请人： Robert Deuchars , Jean-Christophe Berchtold , Joseph Hubert Colles , David Zimlich , Chris Levesque , William David Southcombe , David E. Jones , Scott Yoder , Terry J. Stockert
发明人： Robert Deuchars , Jean-Christophe Berchtold , Joseph Hubert Colles , David Zimlich , Chris Levesque , William David Southcombe , David E. Jones , Scott Yoder , Terry J. Stockert
IPC分类号： G05F3/08 , H03F3/68
CPC分类号： H03F1/0227 , H03F1/0261 , H03F1/0277 , H03F3/195 , H03F3/211 , H03F3/245 , H03F3/602 , H03F3/72 , H03F2200/171 , H03F2200/222 , H03F2200/27 , H03F2200/318 , H03F2200/336 , H03F2200/387 , H03F2200/411 , H03F2200/414 , H03F2200/417 , H03F2200/451 , H03F2200/504 , H03F2200/534 , H03F2200/537 , H03F2200/541 , H03F2203/21106 , H03F2203/21142 , H03F2203/21157
摘要： A direct current (DC)-DC converter having a DC-DC converter semiconductor die and an alpha flying capacitive element is disclosed. The DC-DC converter semiconductor die includes a first series alpha switching element, a second series alpha switching element, a first alpha flying capacitor connection node, which is about over the second series alpha switching element, and a second alpha flying capacitor connection node, which is about over the first series alpha switching element. The alpha flying capacitive element is electrically coupled between the first alpha flying capacitor connection node and the second alpha flying capacitor connection node. By locating the first alpha flying capacitor connection node and the second alpha flying capacitor connection node about over the second series alpha switching element and the first series alpha switching element, respectively, lengths of transient current paths may be minimized, thereby reducing noise and potential interference.
摘要翻译：公开了具有DC-DC转换器半导体管芯和α型飞行电容元件的直流（DC）-DC转换器。 DC-DC转换器半导体管芯包括第一系列α开关元件，第二串联α开关元件，大约在第二串联α开关元件上方的第一α型飞秒电容器连接节点和第二α型飞秒电容器连接节点，这是关于超过第一系列α开关元件。 α飞行电容元件电耦合在第一α型飞秒电容器连接节点和第二α型飞秒电容器连接节点之间。通过分别在第二系列α开关元件和第一系列α开关元件周围定位第一个α飞秒电容器连接节点和第二个α飞秒电容器连接节点，可以将瞬态电流路径的长度最小化，从而降低噪声和潜在干扰。

4. 发明申请

US20100283530A1 Semiconductor Temperature Sensor Using Bandgap Generator Circuit 有权
标题翻译：使用带隙发生器电路的半导体温度传感器
公开(公告)号：US20100283530A1
公开(公告)日：2010-11-11
申请号：US12841362
申请日：2010-07-22
申请人： David Zimlich
发明人： David Zimlich
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： A combined bandgap generator and temperature sensor for an integrated circuit is disclosed. Embodiments of the invention recognize that bandgap generators typically contain at least one temperature-sensitive element for the purpose of cancelling temperature sensitivity out of the reference voltage the bandgap generator produces. Accordingly, this same temperature-sensitive element is used in accordance with the invention as the means for indicating the temperature of the integrated circuit, without the need to fabricate a temperature sensor separate and apart from the bandgap generator. Specifically, in one embodiment, a voltage across a temperature-sensitive junction from a bandgap generator is assessed in a temperature conversion stage portion of the combined bandgap generator and temperature sensor circuit. Assessment of this voltage can be used to produce a voltage- or current-based output indicative of the temperature of the integrated circuit, which output can be binary or analog in nature.
摘要翻译：公开了一种用于集成电路的组合带隙发生器和温度传感器。本发明的实施例认识到，带隙发生器通常包含至少一个温度敏感元件，以便在带隙发生器产生的参考电压之外消除温度敏感性。因此，根据本发明使用相同的温度敏感元件作为用于指示集成电路的温度的装置，而不需要制造分离和分离带隙发生器的温度传感器。具体地，在一个实施例中，在组合带隙发生器和温度传感器电路的温度转换级部分中评估来自带隙发生器的温度敏感结两端的电压。可以使用该电压的评估来产生指示集成电路的温度的基于电压或电流的输出，该输出本质上可以是二进制或模拟的。

5. 发明申请

US20070086250A1 Measure control delay and method having latching circuit integral with delay circuit 有权
公开(公告)号：US20070086250A1
公开(公告)日：2007-04-19
申请号：US11219302
申请日：2005-09-01
申请人： David Zimlich
发明人： David Zimlich
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/222 , G11C11/4076 , H03K5/135
摘要： A measure control delay includes a measuring delay line and a signal generating delay line, each of which include a plurality of series-connected delay units. A digital signal is applied to an initial delay unit in the measuring delay line and it sequentially propagates through the delay units until a second digital signal is received. These outputs are applied to control inputs to the signal generating delay line to control the number of delay units through which a clock signal propagates before being output from a final delay unit. Each of the delay units in the measuring delay line includes a pair of series connected NOR gates. A NOR gate to which the digital signal is initially applied is coupled to a second NOR gate as a flip-flop so that the output of the NOR gate remains constant after the digital signal has been applied to the measuring delay line.

6. 发明申请

US20050146920A1 Access circuit and method for allowing external test voltage to be applied to isolated wells 失效
标题翻译：访问电路和允许外部测试电压施加到隔离井的方法
公开(公告)号：US20050146920A1
公开(公告)日：2005-07-07
申请号：US10748732
申请日：2003-12-29
申请人： David Zimlich
发明人： David Zimlich
IPC分类号： G11C11/22 , G11C29/50
CPC分类号： G11C29/12005 , G11C5/066 , G11C11/401 , G11C29/1201 , G11C29/48 , G11C29/50 , G11C29/50016 , H01L27/0222 , H01L27/10897
摘要： An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective wells coupled between the externally accessible terminal and a respective one of the DRAM wells. The well of the first transistor is coupled to the externally accessible terminal, and the well of the other transistor is coupled to a respective DRAM well. A control circuit applies select signals to gate electrodes of the first and second transistors. The control circuit includes respective shunt transistors that shunt the gate electrodes to the source regions of the first and second transistors when the transistors are turned off to isolate the respective DRAM wells from the external terminal regardless of the magnitude and polarity of a test voltage applied to the externally accessible terminal.
摘要翻译：存取电路选择性地将外部可访问终端耦合到制造相应DRAM阵列的多个隔离DRAM阱中的每一个。每个阱的存取电路包括在耦合在外部可访问的端子和相应的一个DRAM阱之间的各个阱中制造的第一和第二晶体管。第一晶体管的阱耦合到外部可访问的端子，并且另一个晶体管的阱耦合到相应的DRAM阱。控制电路将选择信号施加到第一和第二晶体管的栅电极。控制电路包括各自的分流晶体管，当晶体管关断时，将栅极电极分流到第一和第二晶体管的源极区域，以将各个DRAM阱与外部端子隔离，而不管施加到...的测试电压的大小和极性如何外部可访问终端。

7. 发明授权

US08854019B1 Hybrid DC/DC power converter with charge-pump and buck converter 有权
标题翻译：具有电荷泵和降压转换器的混合DC / DC电源转换器
公开(公告)号：US08854019B1
公开(公告)日：2014-10-07
申请号：US12567318
申请日：2009-09-25
申请人： Chris Levesque , David Zimlich , Jean-Christophe Berchtold
发明人： Chris Levesque , David Zimlich , Jean-Christophe Berchtold
IPC分类号： G05F1/563
CPC分类号： H02M3/07 , H02M1/14 , H02M3/158
摘要： A hybrid Direct Current (DC) to DC converter is disclosed for efficiently converting an input voltage from one level to another. In a preferred embodiment, a dual phase charge pump is combined with a buck converter and a switch controller to provide a converted voltage that is useable to cellular handset circuits based on power amplifier (PA) technology.
摘要翻译：公开了用于将输入电压从一个电平有效地转换到另一个电平的混合直流（DC）到DC转换器。在优选实施例中，双相电荷泵与降压转换器和开关控制器组合以提供可用于基于功率放大器（PA）技术的蜂窝手机电路的转换电压。

8. 发明申请

US20120146695A1 Temperature Compensation Via Power Supply Modification to Produce a Temperature-Independent Delay in an Integrated Circuit 有权
标题翻译：通过电源修改实现温度补偿，以在集成电路中产生与温度无关的延迟
公开(公告)号：US20120146695A1
公开(公告)日：2012-06-14
申请号：US13368606
申请日：2012-02-08
申请人： David Zimlich
发明人： David Zimlich
IPC分类号： H01L35/00 , H03L7/08
CPC分类号： H03L7/0812 , H03L1/022 , H03L7/0814
摘要： A method and circuitry for adjusting the delay of a variable delay line (VDL) in a delay locked loop (DLL) or other delay element or subcircuit on an integrated circuit is disclosed. Such delay circuitry will inherently have a delay which is a function of temperature. Such temperature-dependent delays are compensated for by adjusting the power supply voltage of the VDL, delay element, or subcircuit. Specifically, a temperature sensing stage is used to sense the temperature of the integrated circuit. Information concerning the sensed temperature is sent to a regulator which derives the local power supply voltage from the master power supply voltage, Vcc, of the integrated circuit. If the temperature sensed is relatively high, the regulator increases the local power supply voltage, thus decreasing the delay and offsetting the increase in delay due to temperature.
摘要翻译：公开了一种用于调整延迟锁定环（DLL）中的可变延迟线（VDL）或集成电路上的其他延迟元件或分支电路的延迟的方法和电路。这种延迟电路固有地具有作为温度的函数的延迟。通过调节VDL，延迟元件或子电路的电源电压来补偿这种依赖于温度的延迟。具体地，使用温度感测级来感测集成电路的温度。关于感测温度的信息被发送到从集成电路的主电源电压Vcc导出本地电源电压的调节器。如果检测到的温度相对较高，调节器会增加局部电源电压，从而减少延迟并抵消由于温度引起的延迟增加。

9. 发明申请

US20110260778A1 Semiconductor Temperature Sensor Using Bandgap Generator Circuit 有权
标题翻译：使用带隙发生器电路的半导体温度传感器
公开(公告)号：US20110260778A1
公开(公告)日：2011-10-27
申请号：US13175209
申请日：2011-07-01
申请人： David Zimlich
发明人： David Zimlich
IPC分类号： H01L35/00
CPC分类号： G05F3/30
摘要： A combined bandgap generator and temperature sensor for an integrated circuit is disclosed. Embodiments of the invention recognize that bandgap generators typically contain at least one temperature-sensitive element for the purpose of cancelling temperature sensitivity out of the reference voltage the bandgap generator produces. Accordingly, this same temperature-sensitive element is used in accordance with the invention as the means for indicating the temperature of the integrated circuit, without the need to fabricate a temperature sensor separate and apart from the bandgap generator. Specifically, in one embodiment, a voltage across a temperature-sensitive junction from a bandgap generator is assessed in a temperature conversion stage portion of the combined bandgap generator and temperature sensor circuit. Assessment of this voltage can be used to produce a voltage- or current-based output indicative of the temperature of the integrated circuit, which output can be binary or analog in nature.
摘要翻译：公开了一种用于集成电路的组合带隙发生器和温度传感器。本发明的实施例认识到，带隙发生器通常包含至少一个温度敏感元件，以便在带隙发生器产生的参考电压之外消除温度敏感性。因此，根据本发明使用相同的温度敏感元件作为用于指示集成电路的温度的装置，而不需要制造分离和分离带隙发生器的温度传感器。具体地，在一个实施例中，在组合带隙发生器和温度传感器电路的温度转换级部分中评估来自带隙发生器的温度敏感结两端的电压。可以使用该电压的评估来产生指示集成电路的温度的基于电压或电流的输出，该输出本质上可以是二进制或模拟的。

10. 发明申请

US20070041232A1 Access circuit and method for allowing external test voltage to be applied to isolated wells 有权
标题翻译：访问电路和允许外部测试电压施加到隔离井的方法
公开(公告)号：US20070041232A1
公开(公告)日：2007-02-22
申请号：US11588989
申请日：2006-10-27
申请人： David Zimlich
发明人： David Zimlich
IPC分类号： G11C5/06
CPC分类号： G11C29/12005 , G11C5/066 , G11C11/401 , G11C29/1201 , G11C29/48 , G11C29/50 , G11C29/50016 , H01L27/0222 , H01L27/10897
摘要： An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective wells coupled between the externally accessible terminal and a respective one of the DRAM wells. The well of the first transistor is coupled to the externally accessible terminal, and the well of the other transistor is coupled to a respective DRAM well. A control circuit applies select signals to gate electrodes of the first and second transistors. The control circuit includes respective shunt transistors that shunt the gate electrodes to the source regions of the first and second transistors when the transistors are turned off to isolate the respective DRAM wells from the external terminal regardless of the magnitude and polarity of a test voltage applied to the externally accessible terminal.
摘要翻译：存取电路选择性地将外部可访问终端耦合到制造相应DRAM阵列的多个隔离DRAM阱中的每一个。每个阱的存取电路包括在耦合在外部可访问的端子和相应的一个DRAM阱之间的各个阱中制造的第一和第二晶体管。第一晶体管的阱耦合到外部可访问的端子，并且另一个晶体管的阱耦合到相应的DRAM阱。控制电路将选择信号施加到第一和第二晶体管的栅电极。控制电路包括各自的分流晶体管，当晶体管关断时，将栅极电极分流到第一和第二晶体管的源极区域，以将各个DRAM阱与外部端子隔离，而不管施加到...的测试电压的大小和极性如何外部可访问终端。

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