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1. 发明授权

US07433365B1 System architecture for linking channel banks of a data communication system 有权
标题翻译：用于链接数据通信系统的通道组的系统架构
公开(公告)号：US07433365B1
公开(公告)日：2008-10-07
申请号：US10930101
申请日：2004-08-31
申请人： Richard A. Burch , Neil M. Jensen , Dennis B. McMahan , Timothy David Rochell , Robert James Toth
发明人： Richard A. Burch , Neil M. Jensen , Dennis B. McMahan , Timothy David Rochell , Robert James Toth
IPC分类号： H04J3/16
CPC分类号： H04L12/5601 , H04L49/45 , H04L2012/5606 , H04L2012/5614 , H04L2012/5658 , H04L2012/5679
摘要： A single switch fabric-based, multi-channel bank digital subscriber line access multiplexer includes a master channel bank containing a master switch module in which the switch fabric and a downstream-directed traffic scheduler reside, and one or more expansion channel banks that are linked with the master channel bank by way of upstream and downstream communication links. Distributed among the channel banks are respective policing mechanisms and cell rate control mechanisms that control upstream-directed communications from line card ports of each expansion channel bank to the switch fabric. Downstream data transmissions are locked to network timing, and are scheduled by a centralized scheduling mechanism resident in the master channel bank.
摘要翻译：单个基于交换结构的多通道银行数字用户线路接入复用器包括主信道组，其包含主交换机模块，交换结构和下游定向业务调度器驻留在主交换机模块中，以及连接的一个或多个扩展信道组主通道银行通过上下游通信链路。在信道组之间分布的是相应的监管机制和信元速率控制机制，其控制从每个扩展信道组的线路卡端口到交换结构的上行通信。下行数据传输被锁定到网络定时，并且由驻留在主信道库中的集中式调度机制调度。

2. 发明授权

US07203159B2 Line card-sourced ESF framing protection switch FDL signaling 有权
标题翻译：线卡来源ESF成帧保护开关FDL信令
公开(公告)号：US07203159B2
公开(公告)日：2007-04-10
申请号：US10167012
申请日：2002-06-11
申请人： Dennis B. McMahan , Bradley D. Tidwell
发明人： Dennis B. McMahan , Bradley D. Tidwell
IPC分类号： G01R31/08
CPC分类号： H04J3/14
摘要： A back-up channel line card-installed ESF framing mechanism independently sources an FDL signaling channel for the transport of protection switch signaling information, taking advantage of the fact that DSL multiplexer equipment is capable of accepting and processing ESF framed digital data, including embedded FDL-based signaling information. Upon completion of transport of the FDL-based signaling information, the back-up channel is used for data transport in place of a faulty channel.
摘要翻译：备用信道线路卡安装的ESF成帧机制独立地发送用于传输保护交换机信令信息的FDL信令信道，利用DSL复用器设备能够接受和处理ESF成帧的数字数据，包括嵌入式FDL 的信令信息。在完成基于FDL的信令信息的传输时，备用信道用于数据传输来代替故障信道。

3. 发明授权

US06728649B2 Method and apparatus for removing digital glitches 有权
标题翻译：消除数字毛刺的方法和设备
公开(公告)号：US06728649B2
公开(公告)日：2004-04-27
申请号：US10061848
申请日：2002-02-01
申请人： Dennis B. McMahan , Jason N. Morgan , Timothy D. Rochell
发明人： Dennis B. McMahan , Jason N. Morgan , Timothy D. Rochell
IPC分类号： H03B100
CPC分类号： H03K5/1252
摘要： A method and apparatus for removing glitches, interference or noise from a clock signal are provided by the present invention. In accordance with the invention, a glitch-ridden clock signal is monitored to determine when a transition in the glitch ridden clock signal occurs. When a transition occurs, a counter is initiated in accordance with a second high-speed clock signal. The value of this counter is compared to a compare value. The compare value is selected to approximately equal the expected period of the glitch-ridden clock signal. If the counter value equals the compare value, it is assumed that the transition was a valid transition and the transition is carried through and output as a glitch-free clock signal. However, if a transition occurs before the count value equals the counter compare value, it is assumed that the transition is invalid and no transition is carried to the glitch-free clock output. Thus, the present invention removes glitches from a received clock signal and outputs a glitch-free clock signal.
摘要翻译：本发明提供一种从时钟信号中去除毛刺，干扰或噪声的方法和装置。根据本发明，监视毛刺时钟信号以确定何时发生毛刺时钟信号中的转变。当发生转变时，根据第二高速时钟信号启动计数器。该计数器的值与比较值进行比较。比较值被选择为近似等于毛刺时钟信号的期望周期。如果计数器值等于比较值，则假定转换是有效的转换，并且转换被传送并作为无毛刺时钟信号输出。然而，如果在计数值等于计数器比较值之前发生转换，则假设转换无效，并且没有转移到无毛刺时钟输出。因此，本发明从接收的时钟信号中去除毛刺，并输出无毛刺的时钟信号。

4. 发明授权

US4805191A Modem with improved timing recovery using equalized data 失效
标题翻译：调制解调器使用均衡数据改进了定时恢复
公开(公告)号：US4805191A
公开(公告)日：1989-02-14
申请号：US125312
申请日：1987-11-25
申请人： Richard A. Burch , Dennis B. McMahan , Harry Yedid
发明人： Richard A. Burch , Dennis B. McMahan , Harry Yedid
IPC分类号： H04L7/02 , H04L7/00 , H04B3/04
CPC分类号： H04L7/0054
摘要： In a digital data receiver, it is desirable to use the equalized data for deriving time synchronization information. This invention minimizes timing contention between an equalizer operating at a T/2 rate and a timing recovery circuit which utilizes the output of the equalizer. An interpolator interpolates T1 and T2 data samples from the equalizer and provides data signals R and S equally spaced relative to the peak baud amplitude which can be easily processed by the timing recovery circuit.
摘要翻译：在数字数据接收机中，期望使用均衡数据来导出时间同步信息。本发明使得以T / 2速率工作的均衡器和利用均衡器的输出的定时恢复电路之间的定时争用最小化。内插器从均衡器插入T1和T2数据样本，并提供相对于峰值波特率等距间隔的数据信号R和S，这可以由定时恢复电路容易地处理。

5. 发明授权

US07515591B1 Primary channel bank-resident mechanism for scheduling downstream data transmissions to ports of multiple channel banks 有权
标题翻译：主要渠道银行驻留机制，用于调度到多个信道银行的端口的下行数据传输
公开(公告)号：US07515591B1
公开(公告)日：2009-04-07
申请号：US10930095
申请日：2004-08-31
申请人： Richard A. Burch , Neil M. Jensen , Dennis B. McMahan , Timothy David Rochell
发明人： Richard A. Burch , Neil M. Jensen , Dennis B. McMahan , Timothy David Rochell
IPC分类号： H04L12/28
CPC分类号： H04L49/254 , H04L49/90 , H04L2012/5679
摘要： A data transmission scheduler subsystem for a multi-channel bank communication system architecture contains a plurality of ‘per port’ schedulers. Each per port scheduler is resident in the system's primary channel bank, and is operative to controllably cause customer-destined data, that has been buffered from a communication network into switch fabric storage circuitry of the primary channel bank, to be controllably read out for downlink transmission to associated destination data ports of the channel banks at the destination data ports' data rates.
摘要翻译：用于多通道银行通信系统架构的数据传输调度器子系统包含多个“每端口”调度器。每个端口调度器驻留在系统的主信道组中，并且可操作地将已经从通信网络缓存的客户目的地的数据导入到主信道组的交换结构存储电路中，以被可控地读出用于下行链路以目的地数据端口的数据速率传输到信道组的相关联的目的地数据端口。

6. 发明授权

US07477596B1 Policing engine providing dynamic adjustment of peak and sustained data cell rates and efficient transfer of AAL5 cells 有权
标题翻译：监管引擎提供峰值和持续数据信元速率的动态调整和AAL5细胞的有效转移
公开(公告)号：US07477596B1
公开(公告)日：2009-01-13
申请号：US10930086
申请日：2004-08-31
申请人： Richard A. Burch , Neil M. Jensen , Dennis B. McMahan , Timothy David Rochell
发明人： Richard A. Burch , Neil M. Jensen , Dennis B. McMahan , Timothy David Rochell
IPC分类号： H04J1/16
CPC分类号： H04L12/5601
摘要： A policing engine for use in a telecommunication equipment shelf is operative to control the rate at which customer-sourced ATM packets are passed to buffers associated with different classes of service to which customers may subscribe. The policing engine examines the rate at which ATM cells are supplied to it from the line card ports, whether the cells are AAL5 cells, and how full are the buffers into which the cells are to be written. If cells are supplied to the policing engine at a rate faster than prescribed peak or sustained cell rates, or if the cell buffer begins to fill up, the policing engine controllably discards incoming cells, thereby effectively ‘throttling’ the cell flow rate through it.
摘要翻译：在电信设备机架中使用的监管引擎可操作以控制客户来源的ATM分组被传递到与客户可以订阅的不同服务等级相关联的缓冲器的速率。监管引擎检查ATM单元从线卡端口提供给它的速率，单元格是否为AAL5单元，以及单元格要写入的缓冲区的满载程度。如果细胞以比规定的峰值或持续细胞速率更快的速率提供给治疗引擎，或者如果细胞缓冲液开始填满，则监管引擎可控制地丢弃进入的细胞，从而有效地“调节”细胞流量。

7. 发明授权

US07349420B1 Method and system for preserving channel bank provisioning information when unit location changes within multi-shelf equipment rack 失效
标题翻译：在多架设备机架中单元位置变化时，保留通道库供应信息的方法和系统
公开(公告)号：US07349420B1
公开(公告)日：2008-03-25
申请号：US10930102
申请日：2004-08-31
申请人： Robert James Toth , Neil M. Jensen , Dennis B. McMahan , Timothy David Rochell
发明人： Robert James Toth , Neil M. Jensen , Dennis B. McMahan , Timothy David Rochell
IPC分类号： H04J3/16
CPC分类号： H04L12/2856 , H04L12/2878 , H04L12/40 , H04L29/12839 , H04L61/6022 , H04L61/609 , H04Q1/028 , H04Q1/155
摘要： An inter-channel bank addressing and identification protocol, for use with a multi channel bank, digital subscriber line access multiplexer (DSLAM), enables the control processor of a master channel bank to selectively communicate with control processors of subtended slave channel banks, and allows a subtended slave shelf to retain provisioning information, irrespective of a change in shelf location or removal of a subtended slave shelf between the master shelf and another subtended slave shelf. The inter-channel bank addressing and identification protocol uses a shelf address code that is controllably incremented or decremented during the transport of a packet between the master and a slave shelf. In addition, a shelf address code is assigned each slave shelf during initialization. These two codes enable the master to track which channel bank is in which shelf bay.
摘要翻译：与多频道组，数字用户线接入复用器（DSLAM）一起使用的信道间组合寻址和识别协议使得主信道组的控制处理器能够选择性地与对准的从属信道组的控制处理器通信，并且允许一个对准的从机架，用于保留配置信息，而不管主机架和另一个对准的从机架之间的架子位置的变化或对准的从机架的移除。信道间组合寻址和识别协议使用在主机和从机架之间的分组传输期间可控地递增或递减的机架地址代码。此外，在初始化期间为每个从机架分配货架地址代码。这两个代码使主机可以跟踪哪个通道组在哪个存储区中。

8. 发明授权

US4970715A Modem with improved remote echo location and cancellation 失效
标题翻译：调制解调器具有改进的远程回波位置和取消
公开(公告)号：US4970715A
公开(公告)日：1990-11-13
申请号：US333744
申请日：1989-04-03
申请人： Dennis B. McMahan
发明人： Dennis B. McMahan
IPC分类号： H04B3/23
CPC分类号： H04B3/237
摘要： A modem capable of simultaneously transmitting and receiving data signals over a single communication channel with a remote modem includes a transmitter for converting TX digital data into analog signals for transmission over the channel and a receiver for converting received analog signals into RX digital data. A mechanism identifies a remote echo returning to the modem corresponding to previously transmitted TX digital data. The identifiying mechanism is capable of identifiying a echo originating intermediate between the modem and the remote modem. Another mechanism substantially cancels the identified remote echo. The present invention also encompasses the method of identification and cancellation of remote echos. In addition, remote echo cancellation signals are not combined with received signals until local echo has been substantially cancelled.
摘要翻译：能够通过与远程调制解调器在单个通信信道上同时发送和接收数据信号的调制解调器包括用于将TX数字数据转换成模拟信号以在信道上传输的发射机，以及用于将接收的模拟信号转换为RX数字数据的接收机。一种机制识别与先前发送的TX数字数据相对应的返回到调制解调器的远程回声。识别机制能够识别在调制解调器和远程调制解调器之间产生中间的回波。另一机制基本上消除了所识别的远程回波。本发明还包括远程回声的识别和消除的方法。此外，远程回波消除信号不与接收到的信号组合，直到本地回波基本上被取消为止。

9. 发明授权

US07289532B2 Voice playout buffer for dual-PHY based integrated access device 有权
标题翻译：用于双PHY集成接入设备的语音播放缓冲器
公开(公告)号：US07289532B2
公开(公告)日：2007-10-30
申请号：US10441091
申请日：2003-05-19
申请人： Darrin L. Gieger , Phillip Stone Herron , Dennis B. McMahan
发明人： Darrin L. Gieger , Phillip Stone Herron , Dennis B. McMahan
IPC分类号： H04J3/16
CPC分类号： H04L49/3081 , H04L49/20 , H04L49/30 , H04L2012/5671
摘要： A voice playout buffer for a dual PHY-based integrated access device platform has a plurality of voice signal buffer sections. A respective buffer section has a capacity in excess of the number of digitized voice signal bytes contained in a respective cell-based communication signal. The storage capacity of a buffer section accommodates a communications control processor writing new outgoing digitized voice signal bytes into the first portion of the voice signal buffer section for transport over a TDM communication link, prior to digitized voice signals newly received from the TDM communication link being written into the first portion of the voice signal buffer section.
摘要翻译：用于基于双PHY的集成接入设备平台的语音播出缓冲器具有多个语音信号缓冲器部分。相应的缓冲器部分具有超过相应的基于单元的通信信号中包含的数字化语音信号字节的数量的容量。缓冲器部分的存储容量容纳通信控制处理器，其将新的输出数字化语音信号字节写入到语音信号缓冲器部分的第一部分中，以便在从TDM通信链路新接收的数字化语音信号之前通过TDM通信链路进行传输，写入语音信号缓冲器部分的第一部分。

10. 发明授权

US06445719B1 Method, system and apparatus for reducing synchronization and resynchronization times for systems with pulse stuffing 有权
标题翻译：用于减少具有脉冲填充的系统的同步和重新同步时间的方法，系统和装置
公开(公告)号：US06445719B1
公开(公告)日：2002-09-03
申请号：US09384760
申请日：1999-08-27
申请人： Kevin W. Schneider , Jamie Kelly , Dennis B. McMahan , Marc Kimpe
发明人： Kevin W. Schneider , Jamie Kelly , Dennis B. McMahan , Marc Kimpe
IPC分类号： H04L1250
CPC分类号： H04J3/0605 , H04J3/07 , H04L7/10
摘要： A method, system and apparatus for decreasing the time frame synchronization and resynchronization in a data communication uses an long frame sync word formed by combining a frame sync word with stuff bits, wherein the stuff bits are necessary for timing adjustments.
摘要翻译：用于减少数据通信中的时间帧同步和再同步的方法，系统和装置使用通过组合帧同步字与填充位形成的长帧同步字，其中填充位对于定时调整是必需的。

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