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1. 发明授权

US08769376B2 Memory cell supply voltage control based on error detection 有权
公开(公告)号：US08769376B2
公开(公告)日：2014-07-01
申请号：US13626435
申请日：2012-09-25
申请人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
发明人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Nam Sung Kim , Vivek De
IPC分类号： G11C29/00
CPC分类号： G11C29/42 , G11C11/4125 , G11C11/417 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/12005 , G11C29/50 , G11C2029/0409 , G11C2029/0411 , G11C2029/5004
摘要： Described herein is an apparatus for adjusting a power supply level for a memory cell to improve stability of a memory unit. The apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error.

2. 发明授权

US08640005B2 Method and apparatus for using cache memory in a system that supports a low power state 有权
标题翻译：在支持低功率状态的系统中使用高速缓冲存储器的方法和装置
公开(公告)号：US08640005B2
公开(公告)日：2014-01-28
申请号：US12785182
申请日：2010-05-21
申请人： Christopher B. Wilkerson , Alaa R. Alameldeen , Zeshan A. Chishti , Dinesh Somasekhar , Wei Wu , Shih-Lien Lu
发明人： Christopher B. Wilkerson , Alaa R. Alameldeen , Zeshan A. Chishti , Dinesh Somasekhar , Wei Wu , Shih-Lien Lu
IPC分类号： G11C29/00
CPC分类号： G06F11/1064
摘要： A cache memory system uses multi-bit Error Correcting Code (ECC) with a low storage and complexity overhead. In an embodiment, error correction logic may include a first error correction logic to determine a number of errors in data that is stored in a cache line of a cache memory, and a second error correction logic to receive the data from the first error correction logic if the number of errors is determined to be greater than one and to perform error correction responsive to receipt of the data. The cache memory system can be operated at very low idle power, without dramatically increasing transition latency to and from an idle power state due to loss of state. Other embodiments are described and claimed.
摘要翻译：高速缓冲存储器系统使用具有低存储和复杂度开销的多位错误校正码（ECC）。在一个实施例中，纠错逻辑可以包括：第一纠错逻辑，用于确定存储在高速缓存存储器的高速缓存行中的数据中的错误数;以及第二纠错逻辑，用于从第一纠错逻辑接收数据如果错误的数量被确定为大于1，并且响应于数据的接收执行错误校正。高速缓冲存储器系统可以在非常低的空闲功率下操作，而不会由于状态的损失而急剧增加到空闲功率状态的转换等待时间。描述和要求保护其他实施例。

3. 发明申请

US20130275935A1 PROVIDING TIMING-CLOSED FINFET DESIGNS FROM PLANAR DESIGNS 有权
标题翻译：从平面设计提供定时关闭FINFET设计
公开(公告)号：US20130275935A1
公开(公告)日：2013-10-17
申请号：US13446418
申请日：2012-04-13
申请人： Mahbub Rashed , David Doman , Dinesh Somasekhar , Yan Wang , Yunfei Deng , Navneet Jain , Jongwook Kye , Ali Keshavarzi , Subramani Kengeri , Suresh Venkatesan
发明人： Mahbub Rashed , David Doman , Dinesh Somasekhar , Yan Wang , Yunfei Deng , Navneet Jain , Jongwook Kye , Ali Keshavarzi , Subramani Kengeri , Suresh Venkatesan
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F2217/84
摘要： An approach for providing timing-closed FinFET designs from planar designs is disclosed. Embodiments include: receiving one or more planar cells associated with a planar design; generating an initial FinFET design corresponding to the planar design based on the planar cells and a FinFET model; and processing the initial FinFET design to provide a timing-closed FinFET design. Other embodiments include: determining a race condition associated with a path of the initial FinFET design based on a timing analysis of the initial FinFET design; and increasing delay associated with the path to resolve hold violations associated with the race condition, wherein the processing of the initial FinFET design is based on the delay increase.
摘要翻译：公开了一种从平面设计提供定时关闭的FinFET设计的方法。实施例包括：接收与平面设计相关联的一个或多个平面单元; 基于平面单元和FinFET模型产生对应于平面设计的初始FinFET设计; 并处理初始FinFET设计以提供定时关闭的FinFET设计。其他实施例包括：基于初始FinFET设计的时序分析确定与初始FinFET设计的路径相关联的竞争条件; 以及与解决与竞争条件相关联的持续违规的路径相关联的增加的延迟，其中初始FinFET设计的处理基于延迟增加。

4. 发明授权

US08539303B2 Low overhead error correcting code protection for stored information 有权
标题翻译：存储信息的低开销错误纠正代码保护
公开(公告)号：US08539303B2
公开(公告)日：2013-09-17
申请号：US12973880
申请日：2010-12-20
申请人： Shih-Lien L. Lu , Dinesh Somasekhar
发明人： Shih-Lien L. Lu , Dinesh Somasekhar
IPC分类号： G06F11/00
CPC分类号： H03M13/09 , G06F11/1012 , H03M13/05
摘要： Embodiments of an invention for low overhead error-correcting-code protection for stored information are described are disclosed. In one embodiment, an apparatus includes a data storage structure, a first check value storage structure, a second check value storage structure, and check value generation hardware. The data storage structure is to store a plurality of first data values. The first check value storage structure is to store a plurality of first check values. The second check value storage structure is to store a plurality of second check values. The check value generation hardware is to generate the first check values and the second check values. The first check values provide a first level of error protection for the first data values and the second check values provide a second level of error protection for a plurality of second data values. Each of the plurality of first data value has a first data width, and each of the plurality of second data values has a second data width, the second data width being greater than the first data width. Each of the second data values is a concatenation of one of the first data values and at least another of the first data values.
摘要翻译：公开了用于存储信息的低开销纠错码保护的发明的实施例。在一个实施例中，一种装置包括数据存储结构，第一检查值存储结构，第二检查值存储结构和检查值生成硬件。数据存储结构是存储多个第一数据值。第一检查值存储结构是存储多个第一检查值。第二检查值存储结构是存储多个第二检查值。检查值生成硬件是生成第一检查值和第二检查值。第一检查值为第一数据值提供第一级错误保护，并且第二检查值为多个第二数据值提供第二级别的错误保护。多个第一数据值中的每一个具有第一数据宽度，并且多个第二数据值中的每一个具有第二数据宽度，第二数据宽度大于第一数据宽度。第二数据值中的每一个是第一数据值和第一数据值中的至少另一数据值之一的级联。

5. 发明申请

US20110289380A1 METHOD AND APPARATUS FOR USING CACHE MEMORY IN A SYSTEM THAT SUPPORTS A LOW POWER STATE 有权
标题翻译：在支持低功耗状态的系统中使用高速缓存存储器的方法和装置
公开(公告)号：US20110289380A1
公开(公告)日：2011-11-24
申请号：US12785182
申请日：2010-05-21
申请人： CHRISTOPHER B. WILKERSON , Alaa R. Alameldeen , Zeshan A. Chishti , Dinesh Somasekhar , Wei Wu , Shih-Lien Lu
发明人： CHRISTOPHER B. WILKERSON , Alaa R. Alameldeen , Zeshan A. Chishti , Dinesh Somasekhar , Wei Wu , Shih-Lien Lu
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1064
摘要： A cache memory system is provided that uses multi-bit Error Correcting Code (ECC) with a low storage and complexity overhead. The cache memory system can be operated at very low idle power, without dramatically increasing transition latency to and from an idle power state due to loss of state.
摘要翻译：提供了一种使用具有低存储和复杂度开销的多位错误校正码（ECC）的高速缓冲存储器系统。高速缓冲存储器系统可以在非常低的空闲功率下操作，而不会由于状态的损失而急剧增加到空闲功率状态的转换等待时间。

6. 发明授权

US08030197B2 Recessed channel array transistor (RCAT) in replacement metal gate (RMG) logic flow 有权
标题翻译：嵌入式通道阵列晶体管（RCAT）在替代金属栅极（RMG）逻辑流
公开(公告)号：US08030197B2
公开(公告)日：2011-10-04
申请号：US12435382
申请日：2009-05-04
申请人： Brian S. Doyle , Gilbert Dewey , Ravi Pillarisetty , Nick Lindert , Uday Shah , Dinesh Somasekhar
发明人： Brian S. Doyle , Gilbert Dewey , Ravi Pillarisetty , Nick Lindert , Uday Shah , Dinesh Somasekhar
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823456 , H01L21/82345 , H01L21/823462 , H01L29/4236 , H01L29/49 , H01L29/51 , H01L29/66545 , H01L29/66583 , H01L29/66621 , H01L29/7833 , H01L29/7834
摘要： Embodiments of the invention relate to a method of fabricating logic transistors using replacement metal gate (RMG) logic flow with modified process to form recessed channel array transistors (RCAT) on a common semiconductor substrate. An embodiment comprises forming an interlayer dielectric (ILD) layer on a semiconductor substrate, forming a first recess in the ILD layer of a first substrate region, forming a recessed channel in the ILD layer and in the substrate of a second substrate region, depositing a first conformal high-k dielectric layer in the first recess and a second conformal high-k dielectric layer in the recessed channel, and filling the first recess with a first gate metal and the recessed channel with a second gate metal.
摘要翻译：本发明的实施例涉及使用具有修改过程的替代金属栅（RMG）逻辑流来制造逻辑晶体管的方法，以在公共半导体衬底上形成凹陷沟道阵列晶体管（RCAT）。一个实施例包括在半导体衬底上形成层间绝缘层（ILD）层，在第一衬底区域的ILD层中形成第一凹槽，在第一衬底区域的ILD层和衬底中形成凹陷沟道，第一凹部中的第一共形高k电介质层和凹陷沟道中的第二共形高k电介质层，并且用第一栅极金属填充第一凹槽，并且利用第二栅极金属填充凹陷沟道。

7. 发明申请

US20100181607A1 INCREASING THE SURFACE AREA OF A MEMORY CELL CAPACITOR 有权
标题翻译：增加记忆体电容器的表面积
公开(公告)号：US20100181607A1
公开(公告)日：2010-07-22
申请号：US12749389
申请日：2010-03-29
申请人： Brian S. Doyle , Robert S. Chau , Vivek De , Suman Datta , Dinesh Somasekhar
发明人： Brian S. Doyle , Robert S. Chau , Vivek De , Suman Datta , Dinesh Somasekhar
IPC分类号： H01L27/06
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： Methods and apparatuses to increase a surface area of a memory cell capacitor are described. An opening in a second insulating layer deposited over a first insulating layer on a substrate is formed. The substrate has a fin. A first insulating layer is deposited over the substrate adjacent to the fin. The opening in the second insulating layer is formed over the fin. A first conducting layer is deposited over the second insulating layer and the fin. A third insulating layer is deposited on the first conducting layer. A second conducting layer is deposited on the third insulating layer. The second conducting layer fills the opening. The second conducting layer is to provide an interconnect to an upper metal layer. Portions of the second conducting layer, third insulating layer, and the first conducting layer are removed from a top surface of the second insulating layer.
摘要翻译：描述了增加存储单元电容器的表面积的方法和装置。形成了沉积在基板上的第一绝缘层上的第二绝缘层中的开口。衬底具有翅片。第一绝缘层沉积在邻近鳍片的衬底上。第二绝缘层上的开口形成在鳍上。第一导电层沉积在第二绝缘层和鳍上。第三绝缘层沉积在第一导电层上。第二导电层沉积在第三绝缘层上。第二导电层填充开口。第二导电层是提供与上金属层的互连。从第二绝缘层的顶表面去除第二导电层，第三绝缘层和第一导电层的部分。

8. 发明申请

US20100155801A1 Integrated circuit, 1T-1C embedded memory cell containing same, and method of manufacturing 1T-1C memory cell for embedded memory application 审中-公开
标题翻译：集成电路，含有1T-1C的嵌入式存储单元以及用于嵌入式存储器应用的1T-1C存储单元的制造方法
公开(公告)号：US20100155801A1
公开(公告)日：2010-06-24
申请号：US12317507
申请日：2008-12-22
申请人： Brian S. Doyle , Dinesh Somasekhar , Gilbert Dewey , Satyarth Suri
发明人： Brian S. Doyle , Dinesh Somasekhar , Gilbert Dewey , Satyarth Suri
IPC分类号： H01L29/94 , H01L29/06 , H01L21/8242
CPC分类号： H01L28/90 , H01L27/10894 , H01L27/10897
摘要： An integrated circuit includes a semiconducting substrate (110), electrically conductive layers (120) over the semiconducting substrate, and a capacitor (130) at least partially embedded within the semiconducting substrate such that the capacitor is entirely underneath the electrically conductive layers. A storage node voltage is on an outside layer (132) of the capacitor. In the same or another embodiment, the integrated circuit may act as a 1T-1C embedded memory cell including the semiconducting substrate, an electrically insulating stack (160) over the semiconducting substrate, a transistor (140) including a source/drain region (142) within the semiconducting substrate and a gate region (141) above the semiconducting substrate, a trench (111) extending through the electrically insulating layers and into the semiconducting substrate, a first electrically insulating layer (131) located within the trench, and the capacitor located within the trench interior to the first electrically insulating layer.
摘要翻译：集成电路包括半导体衬底（110），半导体衬底上的导电层（120）和至少部分地嵌入在半导体衬底内的电容器（130），使得电容器完全在导电层的下面。存储节点电压位于电容器的外层（132）上。在相同或另一个实施例中，集成电路可以用作包括半导体衬底的1T-1C嵌入式存储单元，半导体衬底上的电绝缘堆叠（160），包括源极/漏极区域（142）的晶体管（140））和在半导体衬底上方的栅极区（141），延伸穿过电绝缘层并进入半导体衬底的沟槽（111），位于沟槽内的第一电绝缘层（131）和电容器位于第一电绝缘层的沟槽内部。

9. 发明申请

US20100146368A1 PERFORMING MULTI-BIT ERROR CORRECTION ON A CACHE LINE 有权
标题翻译：在缓存行上执行多位错误校正
公开(公告)号：US20100146368A1
公开(公告)日：2010-06-10
申请号：US12331255
申请日：2008-12-09
申请人： Zeshan A. Chishti , Alaa R. Alameldeen , Chris Wilkerson , Wei Wu , Dinesh Somasekhar , Muhammad Khellah , Shih-Lien Lu
发明人： Zeshan A. Chishti , Alaa R. Alameldeen , Chris Wilkerson , Wei Wu , Dinesh Somasekhar , Muhammad Khellah , Shih-Lien Lu
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/2921 , G06F11/1064 , H03M13/1102 , H03M13/13 , H03M13/15 , H03M13/1515 , H03M13/2906 , H03M13/2918
摘要： A processor may comprise a cache, which may be divided into a first and second section while the processor operates in a low-power mode. A cache line of the first section may be fragmented into segments. A first encoder may generate first data bits and check bits while encoding a first portion of a data stream and a second encoder may, separately, generate second data bits and check bits while encoding a second portion of the data stream. The first data bits may be stored in a first segment of the first section and the check bits in a first portion of the second section that is associated with the first segment. The first decoder may correct errors in multiple bit positions within the first data bits using the check bits stored in the first portion and the second decoder may, separately, decode the second data bits using the second set of check bits.
摘要翻译：处理器可以包括高速缓存，其可以在处理器以低功率模式操作时被分成第一和第二部分。第一部分的高速缓存行可以被分段成段。第一编码器可以在对数据流的第一部分进行编码的同时产生第一数据位和校验位，并且第二编码器可以分别在编码数据流的第二部分时生成第二数据位和校验位。第一数据位可以存储在第一部分的第一部分中，并且与第一部分相关联的第二部分的第一部分中的校验位。第一解码器可以使用存储在第一部分中的校验位来校正第一数据位中的多位位置中的错误，并且第二解码器可以单独地使用第二组校验位对第二数据位进行解码。

10. 发明申请

US20080237796A1 Increasing the surface area of a memory cell capacitor 有权
标题翻译：增加存储单元电容器的表面积
公开(公告)号：US20080237796A1
公开(公告)日：2008-10-02
申请号：US11731193
申请日：2007-03-30
申请人： Brian S. Doyle , Robert S. Chau , Vivek De , Suman Datta , Dinesh Somasekhar
发明人： Brian S. Doyle , Robert S. Chau , Vivek De , Suman Datta , Dinesh Somasekhar
IPC分类号： H01L29/92 , H01L21/20
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： Methods and apparatuses to increase a surface area of a memory cell capacitor are described. An opening in a second insulating layer deposited over a first insulating layer on a substrate is formed. The substrate has a fin. A first insulating layer is deposited over the substrate adjacent to the fin. The opening in the second insulating layer is formed over the fin. A first conducting layer is deposited over the second insulating layer and the fin. A third insulating layer is deposited on the first conducting layer. A second conducting layer is deposited on the third insulating layer. The second conducting layer fills the opening. The second conducting layer is to provide an interconnect to an upper metal layer. Portions of the second conducting layer, third insulating layer, and the first conducting layer are removed from a top surface of the second insulating layer.
摘要翻译：描述了增加存储单元电容器的表面积的方法和装置。形成了沉积在基板上的第一绝缘层上的第二绝缘层中的开口。衬底具有翅片。第一绝缘层沉积在邻近鳍片的衬底上。第二绝缘层上的开口形成在鳍上。第一导电层沉积在第二绝缘层和鳍上。第三绝缘层沉积在第一导电层上。在第三绝缘层上沉积第二导电层。第二导电层填充开口。第二导电层是提供与上金属层的互连。从第二绝缘层的顶表面去除第二导电层，第三绝缘层和第一导电层的部分。

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