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    • 3. 发明申请
    • Multi level flash memory device and program method
    • 多级闪存设备和程序方法
    • US20050190603A1
    • 2005-09-01
    • US11021181
    • 2004-12-22
    • Seung-Keun LeeDong-Ho Park
    • Seung-Keun LeeDong-Ho Park
    • G11C16/00G11C11/34G11C11/56G11C16/10G11C16/34
    • G11C11/5628G11C16/10G11C16/3454G11C16/3459G11C2211/5621
    • We describe a multi level flash memory device and program method. The multi level flash memory device includes a plurality of memory cells, each storing an amount of charge indicative of more than two possible states and control circuitry coupled to the memory cells. The control circuitry to applying a programming voltage alternating with a verification voltage to the memory cells until all are at a desired state and applying at least one additional programming voltage to the cells in a highest state without applying a verification voltage. The method includes applying at least one programming pulse to the cells, verifying that each cell has reached the desired state, selecting the cells that are programmed for a highest state, and applying at least one additional programming pulse to the selected cells without further verifying their state.
    • 我们描述一个多级闪存设备和程序方法。 多级闪存器件包括多个存储器单元,每个存储器单元存储指示多于两种可能状态的电荷量以及耦合到存储器单元的控制电路。 控制电路,用于将编程电压与验证电压交替地施加到存储器单元,直到全部处于期望状态,并且在不施加验证电压的情况下以最高状态向单元施加至少一个附加编程电压。 该方法包括向单元施加至少一个编程脉冲,验证每个单元已经达到期望状态,选择被编程为最高状态的单元,以及向选定单元施加至少一个附加编程脉冲,而不进一步验证它们 州。
    • 4. 发明授权
    • Non-volatile semiconductor memory device
    • 非易失性半导体存储器件
    • US06466478B1
    • 2002-10-15
    • US09847115
    • 2001-05-01
    • Dong-Ho Park
    • Dong-Ho Park
    • G11C1604
    • G11C16/08G11C29/70
    • A NOR-type flash memory device includes a global decoder circuit that is coupled to global wordlines. The global decoder circuit drives the global wordlines using wordline voltages that will be applied to local wordlines in each operation mode, and has wordline select switches each corresponding to the global wordlines. A local decoder circuit couples the local wordlines to the global wordlines in response to a sector select signal, and a sector generates a control signal in accordance with address information for selecting a memory cell array. A switch circuit includes a plurality of depletion MOS transistors each being coupled between corresponding first and second wordline. The depletion MOS transistors are commonly controlled by a control signal. Each of the wordline select switches is made of two NMOS transistors.
    • NOR型闪存器件包括耦合到全局字线的全局解码器电路。 全局解码器电路使用将在每个操作模式下应用于本地字线的字线电压来驱动全局字线,并且具有分别对应于全局字线的字线选择开关。 本地解码器电路响应于扇区选择信号将本地字线耦合到全局字线,并且扇区根据用于选择存储单元阵列的地址信息产生控制信号。 开关电路包括多个耗尽型MOS晶体管,每个耗尽型MOS晶体管都耦合在对应的第一和第二字线之间。 耗尽型MOS晶体管通常由控制信号控制。 每个字线选择开关由两个NMOS晶体管组成。
    • 5. 发明授权
    • Steering wheel having a collapsible hub
    • 方向盘有一个可折叠集线器
    • US6003406A
    • 1999-12-21
    • US982234
    • 1997-12-01
    • Ju-Young LeeDong-Ho Park
    • Ju-Young LeeDong-Ho Park
    • B62D1/10B60R21/05B60R21/203B62D1/11F16F7/00F16F7/12B62D1/04
    • B62D1/11B60R21/05F16F7/123B60R21/2035Y10T74/20834
    • A steering wheel having a collapsible hub, the steering wheel comprising a wheel 100 having a rim 140, a plurality of spokes 130 connected with the rim 140 and a lower plate 150 having edges and connected with the spokes 130 at the middle of the wheel 100, the edges of the lower plate forming a shape of an open box; a back plate 200 fixed to the said plurality of spokes 130 of the wheel 100 and having an escape hole 220 opened from the middle to one side of the plate 200; an upper plate 300 having first and second vertical surfaces 320 and 330 fixed to the back plate 200 and a horizontal surface 340 connecting the vertical surfaces 320 and 330 to form a space between the back plate 200 and the upper plate 300; and a hub cover 400 installed on the wheel 100 for covering the upper plate 300, so the upper plate 300 collapses to absorb impact of a driver in a car accident.
    • 具有可折叠轮毂的方向盘,所述方向盘包括具有轮辋140的轮100,与轮辋140连接的多个辐条130和具有边缘并与轮100中间的轮辐130连接的下板150 ,所述下板的边缘形成打开的盒子的形状; 固定到车轮100的所述多个轮辐130的背板200,并且具有从板200的中间向一侧开口的排出孔220; 具有固定到背板200的第一和第二垂直表面320和330的上板300和连接垂直表面320和330以在后板200和上板300之间形成空间的水平表面340; 以及安装在车轮100上以覆盖上板300的轮毂盖400,因此上板300塌陷以吸收驾驶员在车祸中的冲击。
    • 10. 发明申请
    • METHOD FOR FORMING SILICIDE IN SEMICONDUCTOR DEVICE
    • 在半导体器件中形成硅化物的方法
    • US20100163938A1
    • 2010-07-01
    • US12648210
    • 2009-12-28
    • Dong-Ho Park
    • Dong-Ho Park
    • H01L29/45H01L21/762H01L21/3205H01L29/78
    • H01L21/28518H01L21/28052H01L29/665H01L29/6659H01L29/7833
    • A method of forming a silicide in a semiconductor device includes: forming a poly gate on and/or over the upper portion of a silicon substrate having an active area and an STI formed therein; forming a spacer wall on and/or over both sidewalls of the poly gate; forming source/drain by performing high-concentration ion implantation; forming a silicide blocking pattern on and/or over both sidewalls of the spacer wall and on the STI; forming a multilayer silicide material on and/or over substantially the entire surface of the silicon substrate having the silicide blocking pattern formed thereover; and performing an RTA process on the multilayer silicide material to form a silicide by reaction between the poly gate and the source/drain electrode.
    • 在半导体器件中形成硅化物的方法包括:在其中形成有活性区域和STI的硅衬底的上部和/或上方形成多晶硅栅极; 在所述多晶硅栅极的两个侧壁上和/或上方形成间隔壁; 通过进行高浓度离子注入形成源极/漏极; 在间隔壁和STI的两个侧壁上和/或上方形成硅化物阻挡图案; 在其上形成有硅化物阻挡图案的硅衬底的基本整个表面上和/或上方形成多层硅化物材料; 以及通过所述多晶硅栅极和所述源极/漏极之间的反应在所述多层硅化物材料上进行RTA工艺以形成硅化物。