专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08652266B2 Method and apparatus for surface treatment of semiconductor substrates using sequential chemical applications 有权
标题翻译：使用顺序化学应用对半导体衬底进行表面处理的方法和装置
公开(公告)号：US08652266B2
公开(公告)日：2014-02-18
申请号：US12212559
申请日：2008-09-17
申请人： Katrina Mikhaylichenko , Yizhak Sabba , Dragan Podlesnik
发明人： Katrina Mikhaylichenko , Yizhak Sabba , Dragan Podlesnik
IPC分类号： B08B3/00
CPC分类号： H01L21/67051 , H01L21/02071 , H01L21/6704 , H01L21/67075 , H01L21/67253 , H01L22/12 , H01L22/20
摘要： A system and method for removing polymer residue from around a metal gate structure formed on a surface of a substrate during a post-etch cleaning operation includes determining a plurality of process parameters associated with the metal gate structure and the polymer residue to be removed. A plurality of fabrication layers define the metal gate structure and the process parameters define characteristics of the fabrication layers and the polymer residue. A first cleaning chemistry and second cleaning chemistry are identified and a plurality of application parameters associated with the first and second cleaning chemistries are defined based on the process parameters. The first and second application chemistries are applied sequentially in a controlled manner using the application parameters to substantial remove the polymer residue while preserving the structural integrity of the gate structure.
摘要翻译：在蚀刻前清洁操作期间从形成在基板的表面上的金属栅极结构周围除去聚合物残留物的系统和方法包括确定与金属栅极结构和待除去的聚合物残余物相关联的多个工艺参数。多个制造层限定了金属栅极结构，并且工艺参数限定了制造层和聚合物残余物的特性。识别第一清洁化学品和第二清洁化学品，并且基于过程参数来定义与第一和第二清洁化学品相关联的多个施用参数。使用应用参数以受控的方式顺序施加第一和第二施用化学物质，以显着除去聚合物残余物，同时保持栅极结构的结构完整性。

2. 发明授权

US06383941B1 Method of etching organic ARCs in patterns having variable spacings 失效
标题翻译：在具有可变间隔的图案中蚀刻有机ARC的方法
公开(公告)号：US06383941B1
公开(公告)日：2002-05-07
申请号：US09611085
申请日：2000-07-06
申请人： Meihua Shen , Kenju Nishikido , Jeffrey D. Chinn , Dragan Podlesnik
发明人： Meihua Shen , Kenju Nishikido , Jeffrey D. Chinn , Dragan Podlesnik
IPC分类号： H01L2100
CPC分类号： H01L21/31138 , H01L21/0276 , H01L21/3065
摘要： The present disclosure relates to semiconductor processing, and to the plasma etching of organic layers, and in particular antireflective coating layers. We have discovered a particular combination of gases useful in producing chemically reactive plasma species, which provides unexpected control over etched feature critical dimension, etch profile, and uniformity of etch across a substrate surface, despite a difference in the spacing of etched features over the substrate surface. The combination of gases which produces chemically reactive plasma species consists essentially of CxHyFz, a bromine-comprising compound (which is typically HBr), and O2, where x ranges from 1 to 4, y ranges from 0 to 3, and z ranges from 1 to 10. Oxygen atoms may be substituted for hydrogen atoms in the CxHyFz compound to a limited extent Essentially inert gases which do not produce chemically reactive species may be added to the combination of etchant-species producing gases. A combination of CF4/HBr/O2 has been demonstrated to work well. With this combination of plasma source gases, critical Dimension (CD) uniformity control across the surface of the substrate is generally improved by using a volumetric ratio of CxHyFz:HBr ranging from about 2:1 to about 5:1, with a range of about 3:1 to about 4:1 being preferred. An increased plasma density also helps improve CD uniformity control. The volumetric ratio of (CxHyFz+HBr):O2 should range between about 1:1 to 5:1, with a range of about 2:1 to about 3:1 being preferred.
摘要翻译：本公开涉及半导体处理，以及有机层的等离子体蚀刻，特别是抗反射涂层。我们已经发现了可用于生产化学反应性等离子体物质的特定气体组合，尽管蚀刻特征在衬底上的间隔有差异，但是它们对蚀刻特征临界尺寸，蚀刻轮廓以及衬底表面上的蚀刻均匀性提供了意想不到的控制表面。产生化学反应性等离子体物质的气体的组合基本上由CxHyFz，含溴化合物（通常为HBr）和O 2组成，其中x为1至4，y为0至3，z的范围为1 氧原子可以在有限的程度上代替CxHyFz化合物中的氢原子。基本上不产生化学反应性物质的惰性气体可以添加到产生蚀刻剂的气体组合中。 CF4 / HBr / O2的组合已被证明是有效的。通过这种等离子体源气体的组合，通常通过使用C 2 H 4 F 5 :H 2 O的体积比约2:1至约5:1的体积比来改善基底表面上的临界尺寸（CD）均匀性控制，其范围为约优选3:1至约4:1。增加的等离子体密度也有助于改善CD均匀性控制。（C x H y F z + HBr）：O 2的体积比应在约1:1至5:1之间，优选约2:1至约3:1的范围。

3. 发明授权

US06380095B1 Silicon trench etch using silicon-containing precursors to reduce or avoid mask erosion 失效
标题翻译：使用含硅前体进行硅沟槽蚀刻，以减少或避免掩模侵蚀
公开(公告)号：US06380095B1
公开(公告)日：2002-04-30
申请号：US09716074
申请日：2000-11-16
申请人： Wei Liu , Yiqiong Wang , Maocheng Li , Anisul Khan , Shaoher Pan , Dragan Podlesnik
发明人： Wei Liu , Yiqiong Wang , Maocheng Li , Anisul Khan , Shaoher Pan , Dragan Podlesnik
IPC分类号： H01L21302
CPC分类号： H01L21/3065
摘要： The present invention pertains to an etch chemistry and method useful for the etching of silicon surfaces. The method is particularly useful in the deep trench etching of silicon where profile control is important. In the case of deep trench etching, at least a portion of the substrate toward the bottom of the trench is etched using a combination of reactive gases including a fluorine-containing compound which does not contain silicon (FC); a silicon-containing compound (SC) which does not contain fluorine; and oxygen (O2).
摘要翻译：本发明涉及用于蚀刻硅表面的蚀刻化学和方法。该方法在硅的深沟槽蚀刻中特别有用，其中轮廓控制是重要的。在深沟槽蚀刻的情况下，使用包含不含硅（FC）的含氟化合物的反应性气体的组合来蚀刻朝向沟槽底部的至少一部分衬底; 不含氟的含硅化合物（SC）; 和氧气（O2）。

4. 发明授权

US06235643B1 Method for etching a trench having rounded top and bottom corners in a silicon substrate 失效
标题翻译：蚀刻在硅衬底中具有圆形顶角和底角的沟槽的方法
公开(公告)号：US06235643B1
公开(公告)日：2001-05-22
申请号：US09371966
申请日：1999-08-10
申请人： David Mui , Dragan Podlesnik , Wei Liu , Gene Lee , Nam-Hun Kim , Jeff Chinn
发明人： David Mui , Dragan Podlesnik , Wei Liu , Gene Lee , Nam-Hun Kim , Jeff Chinn
IPC分类号： H01L2100
CPC分类号： H01L21/76232 , H01L21/3065 , H01L21/3081
摘要： The present invention provides straight forward methods for plasma etching a trench having rounded top corners, or rounded bottom corners, or both in a silicon substrate. A first method for creating a rounded top corner on the etched silicon trench comprises etching both an overlying silicon oxide layer and an upper portion of the silicon substrate during a “break-through” step which immediately precedes the step in which the silicon trench is etched. The plasma feed gas for the break-through step comprises carbon and fluorine. In this method, the photoresist layer used to pattern the etch stack is preferably not removed prior to the break-through etching step. Subsequent to the break-through step, a trench is etched to a desired depth in the silicon substrate using a different plasma feed gas composition. A second method for creating a rounded top corner on the etched silicon trench comprises formation of a built-up extension on the sidewall of an overlying patterned silicon nitride hard mask during etch (break-through) of a silicon oxide adhesion layer which lies between the hard mask and a silicone substrate. The built-up extension upon the silicon nitride sidewall acts as a sacrificial masking material during etch of the silicon trench, delaying etching of the silicon at the outer edges of the top of the trench. This permits completion of trench etching with delayed etching of the top corner of the trench and provides a more gentle rounding (increased radius) at the top corners of the trench. During the etching of the silicon trench to its final dimensions, it is desirable to round the bottom corners of the finished silicon trench. We have discovered that a more rounded bottom trench corner is obtained using a two-step silicon etch process where the second step of the process is carried out at a higher process chamber pressure than the first step.
摘要翻译：本发明提供了用于在硅衬底中等离子体蚀刻具有圆形顶角或圆形底角或两者的沟槽的直接方法。用于在蚀刻的硅沟槽上形成圆角顶角的第一种方法包括：在“穿透”步骤期间蚀刻覆盖硅氧化物层和硅衬底的上部两者之间，其中硅裂纹之前的步骤。用于穿透步骤的等离子体进料气体包括碳和氟。在该方法中，用于图案化蚀刻叠层的光致抗蚀剂层优选在穿透蚀刻步骤之前不被去除。在突破步骤之后，使用不同的等离子体进料气体组合物将沟槽蚀刻到硅衬底中的所需深度。用于在蚀刻的硅沟槽上产生圆角顶角的第二种方法包括在位于第二层之间的氧化硅粘合层的蚀刻（穿透）期间在覆盖的图案化氮化硅硬掩模的侧壁上形成积层延伸。硬面罩和硅胶基材。在硅氮化物侧壁上的累积延伸在硅沟槽的蚀刻期间用作牺牲掩模材料，延迟在沟槽顶部的外边缘处的硅的蚀刻。这允许通过延迟蚀刻沟槽的顶角完成沟槽蚀刻，并且在沟槽的顶角提供更温和的圆化（增加的半径）。在将硅沟槽蚀刻到其最终尺寸期间，期望圆形完成的硅沟槽的底角。我们已经发现，使用两步硅蚀刻工艺获得更圆的底部沟槽角，其中该工艺的第二步骤在比第一步高的处理室压力下进行。

5. 发明申请

US20100018553A1 METHOD AND APPARATUS FOR SURFACE TREATMENT OF SEMICONDUCTOR SUBSTRATES USING SEQUENTIAL CHEMICAL APPLICATIONS 有权
标题翻译：使用顺序化学应用的表面处理半导体基板的方法和装置
公开(公告)号：US20100018553A1
公开(公告)日：2010-01-28
申请号：US12212559
申请日：2008-09-17
申请人： Katrina Mikhaylichenko , Yizhak Sabba , Dragan Podlesnik
发明人： Katrina Mikhaylichenko , Yizhak Sabba , Dragan Podlesnik
IPC分类号： B08B7/04 , B08B13/00
CPC分类号： H01L21/67051 , H01L21/02071 , H01L21/6704 , H01L21/67075 , H01L21/67253 , H01L22/12 , H01L22/20
摘要： A system and method for removing polymer residue from around a metal gate structure formed on a surface of a substrate during a post-etch cleaning operation includes determining a plurality of process parameters associated with the metal gate structure and the polymer residue to be removed. A plurality of fabrication layers define the metal gate structure and the process parameters define characteristics of the fabrication layers and the polymer residue. A first cleaning chemistry and second cleaning chemistry are identified and a plurality of application parameters associated with the first and second cleaning chemistries are defined based on the process parameters. The first and second application chemistries are applied sequentially in a controlled manner using the application parameters to substantial remove the polymer residue while preserving the structural integrity of the gate structure.
摘要翻译：在蚀刻前清洁操作期间从形成在基板的表面上的金属栅极结构周围除去聚合物残留物的系统和方法包括确定与金属栅极结构和待除去的聚合物残余物相关联的多个工艺参数。多个制造层限定了金属栅极结构，并且工艺参数限定了制造层和聚合物残余物的特性。识别第一清洁化学品和第二清洁化学品，并且基于过程参数来定义与第一和第二清洁化学品相关联的多个施用参数。使用应用参数以受控的方式顺序施加第一和第二施用化学物质，以显着除去聚合物残余物，同时保持栅极结构的结构完整性。

6. 发明申请

US20070020937A1 Etch chamber with dual frequency biasing sources and a single frequency plasma generating source 审中-公开
标题翻译：具有双频偏压源和单频等离子体发生源的蚀刻室
公开(公告)号：US20070020937A1
公开(公告)日：2007-01-25
申请号：US11502614
申请日：2006-08-09
申请人： Jin-Yuan Chen , Frank Hooshdaran , Dragan Podlesnik
发明人： Jin-Yuan Chen , Frank Hooshdaran , Dragan Podlesnik
IPC分类号： H01L21/302
CPC分类号： H01J37/321 , H01J37/32706
摘要： A method and apparatus for selectively controlling a plasma in a processing chamber during wafer processing. The method includes providing process gasses into the chamber over a wafer to be processed, and providing high frequency RF power to a plasma generating element and igniting the process gases into the plasma. Modulated RF power is coupled to a biasing element, and wafer processing is performed according to a particular processing recipe. The apparatus includes a biasing element disposed in the chamber and adapted to support a wafer, and a plasma generating element disposed over the biasing element and wafer. A first power source is coupled to the plasma generating element, and a second power source is coupled to the biasing element. A third power source is coupled to the biasing element, wherein the second and third power sources provide a modulated signal to the biasing element.
摘要翻译：一种用于在晶片处理期间选择性地控制处理室中的等离子体的方法和装置。该方法包括在要处理的晶片上的室中提供过程气体，以及向等离子体产生元件提供高频RF功率，并将工艺气体点燃到等离子体中。调制的RF功率耦合到偏置元件，并且根据特定的处理配方执行晶片处理。该装置包括设置在腔室中并适于支撑晶片的偏置元件和设置在偏置元件和晶片上方的等离子体产生元件。第一电源耦合到等离子体发生元件，并且第二电源耦合到偏置元件。第三电源耦合到偏置元件，其中第二和第三电源向偏置元件提供调制信号。

7. 发明授权

US06827869B2 Method of micromachining a multi-part cavity 失效
标题翻译：微加工多部分腔体的方法
公开(公告)号：US06827869B2
公开(公告)日：2004-12-07
申请号：US10194167
申请日：2002-07-11
申请人： Dragan Podlesnik , Thorsten Lill , Jeff Chinn , Shaoher X. Pan , Anisul Khan , Maocheng Li , Yiqiong Wang
发明人： Dragan Podlesnik , Thorsten Lill , Jeff Chinn , Shaoher X. Pan , Anisul Khan , Maocheng Li , Yiqiong Wang
IPC分类号： H01L21302
CPC分类号： H01L27/1087 , B81B2201/052 , B81B2203/0315 , B81B2203/033 , B81C1/00119 , B81C2201/016 , H01L21/3065 , H01L21/3086
摘要： The present disclosure pertains to our discovery of a particularly efficient method for etching a multi-part cavity in a substrate. The method provides for first etching a shaped opening, depositing a protective layer over at least a portion of the inner surface of the shaped opening, and then etching a shaped cavity directly beneath and in continuous communication with the shaped opening. The protective layer protects the etch profile of the shaped opening during etching of the shaped cavity, so that the shaped opening and the shaped cavity can be etched to have different shapes, if desired. In particular embodiments of the method of the invention, lateral etch barrier layers and/or implanted etch stops are also used to direct the etching process. The method of the invention can be applied to any application where it is necessary or desirable to provide a shaped opening and an underlying shaped cavity having varying shapes. The method is also useful whenever it is necessary to maintain tight control over the dimensions of the shaped opening.
摘要翻译：本公开涉及我们发现用于蚀刻衬底中的多部分空腔的特别有效的方法。该方法提供了首先蚀刻成形开口，在成形开口的内表面的至少一部分上沉积保护层，然后直接在成形开口下面蚀刻成形腔，并与成形开口连续连通。保护层在蚀刻成形腔体期间保护成形开口的蚀刻轮廓，从而如果需要，成形开口和成形腔体可以被蚀刻以具有不同的形状。在本发明方法的特定实施例中，横向蚀刻阻挡层和/或注入的蚀刻停止点也用于引导蚀刻工艺。本发明的方法可以应用于需要或期望提供具有不同形状的成形开口和下面的成形腔的任何应用。只要需要对成形开口的尺寸进行严格控制，该方法也是有用的。

8. 发明授权

US06270634B1 Method for plasma etching at a high etch rate 失效
标题翻译：用于以高蚀刻速率进行等离子体蚀刻的方法
公开(公告)号：US06270634B1
公开(公告)日：2001-08-07
申请号：US09430798
申请日：1999-10-29
申请人： Ajay Kumar , Anisul Khan , Jeffrey D Chinn , Dragan Podlesnik
发明人： Ajay Kumar , Anisul Khan , Jeffrey D Chinn , Dragan Podlesnik
IPC分类号： C23C1434
CPC分类号： H01L21/67069 , H01J37/321 , H01J37/32935 , H01L21/3065
摘要： This invention is directed to a method for rapid plasma etching of materials which are difficult to etch at a high rate. The method is particularly useful in plasma etching silicon nitride layers more than five microns thick. The method includes the use of a plasma source gas that includes an etchant gas and a sputtering gas. Two separate power sources are used in the etching process and the power to each power source as well as the ratio between the flow rates of the etchant gas and sputtering gas can be advantageously adjusted to obtain etch rates of silicon nitride greater than two microns per minute. Additionally, an embodiment of the method of the invention provides a two etch step process which combines a high etch rate process with a low etch rate process to achieve high throughput while minimizing the likelihood of damage to underlying layers. The first etch step of the two-step method provides a high etch rate of about two microns per minute to remove substantially all of a layer to be etched. In the second step, a low etch rate process having an etch rate below about two microns per minute is used to remove any residual material not removed by the first etch step.
摘要翻译：本发明涉及用于快速等离子体蚀刻难以高速蚀刻的材料的方法。该方法在等离子体蚀刻中超过5微米厚的氮化硅层特别有用。该方法包括使用包括蚀刻剂气体和溅射气体的等离子体源气体。在蚀刻工艺中使用两个单独的电源，并且可以有利地调整蚀刻剂气体和溅射气体的流量之间的比例，以获得大于每分钟2微米的氮化硅的蚀刻速率。另外，本发明的方法的一个实施例提供了两个蚀刻步骤方法，其将高蚀刻速率工艺与低蚀刻速率工艺组合以实现高通量，同时最小化对下层的损伤的可能性。两步法的第一蚀刻步骤提供了每分钟约2微米的高蚀刻速率，以便基本上除去所有待蚀刻的层。在第二步骤中，使用蚀刻速率低于每分钟约2微米的低蚀刻速率工艺来去除通过第一蚀刻步骤未被去除的任何残留材料。

9. 发明授权

US06180533B2 Method for etching a trench having rounded top corners in a silicon substrate 失效
标题翻译：用于蚀刻在硅衬底中具有圆形顶角的沟槽的方法
公开(公告)号：US06180533B2
公开(公告)日：2001-01-30
申请号：US09545700
申请日：2000-04-07
申请人： Alok Jain , Michelle Siew Mooi Low , Gang Zou , David Mui , Dragan Podlesnik , Wei Liu
发明人： Alok Jain , Michelle Siew Mooi Low , Gang Zou , David Mui , Dragan Podlesnik , Wei Liu
IPC分类号： H01L2100
CPC分类号： H01L21/3065 , H01L21/3081 , H01L21/76232
摘要： The present disclosure includes a method of plasma etching a trench having rounded top corners in a silicon substrate. One embodiment includes the following general steps: a) providing a semiconductor structure comprising a hard masking layer, overlying a silicon substrate; b) plasma etching through said hard masking layer and any additional underlying layers overlying said silicon substrate using at least one plasma feed gas which does not provide polymer deposition on surfaces of said semiconductor structure during etching; where said plasma etching exposes a face of said silicon substrate; and c) plasma etching at least a first portion of a trench into said silicon substrate using reactive species generated from a feed gas comprising a source of fluorine, a source of carbon, a source of hydrogen, and a source of high energy species which provide physical bombardment of said silicon substrate. Top corner rounding is effected by deposition of a thin layer of polymer on a top corner of the trench during etching of the first portion of the trench, resulting in the formation of a rounded “shoulder” at the top corner of the trench. Typically a layer of silicon oxide overlies at least a portion of the silicon substrate surface. The method described provides excellent critical dimension control over the active area of a transistor produced using the method and reduces the need to remove polymer from substrate and reactor surfaces after etching of the silicon trench.
摘要翻译：本公开内容包括等离子体蚀刻在硅衬底中具有圆形顶角的沟槽的方法。一个实施例包括以下一般步骤：a）提供包括覆盖硅衬底的硬掩模层的半导体结构; b）使用至少一种在蚀刻期间不提供聚合物沉积在所述半导体结构的表面上的等离子体进料气体来等离子体蚀刻通过所述硬掩模层和覆盖所述硅衬底的任何附加的底层; 其中所述等离子体蚀刻暴露所述硅衬底的表面; 以及c）使用由包含氟源，碳源，氢源和高能量源的进料气体产生的反应性物质将沟槽的至少第一部分等离子体蚀刻到所述硅基板中，所述源提供所述硅衬底的物理轰击。通过在沟槽的第一部分的蚀刻期间在沟槽的顶角上沉积聚合物薄层来实现顶角圆角化，导致在沟槽的顶角形成圆形“肩部”。通常，氧化硅层覆盖硅衬底表面的至少一部分。所描述的方法提供了使用该方法制造的晶体管的有源面积的优异临界尺寸控制，并且减少了在蚀刻硅沟槽之后从衬底和反应器表面除去聚合物的需要。

10. 发明授权

US5801386A Apparatus for measuring plasma characteristics within a semiconductor wafer processing system and a method of fabricating and using same 失效
标题翻译：用于测量半导体晶片处理系统内的等离子体特性的装置及其制造和使用方法
公开(公告)号：US5801386A
公开(公告)日：1998-09-01
申请号：US653212
申请日：1996-05-28
申请人： Valentin N. Todorov , Yoshi Tanase , Xue-Yu Qian , Arthur H. Sato , Peter Loewenhardt , Yan Ye , Shaoher X. Pan , Dragan Podlesnik
发明人： Valentin N. Todorov , Yoshi Tanase , Xue-Yu Qian , Arthur H. Sato , Peter Loewenhardt , Yan Ye , Shaoher X. Pan , Dragan Podlesnik
IPC分类号： H01J37/32 , H01J37/244
CPC分类号： H01J37/32935
摘要： Apparatus for measuring plasma characteristics within a semiconductor wafer processing system and a method of fabricating and using the apparatus. The apparatus contains a first insulator layer upon which one or more conductive collector pads are formed by patterning and etching a copper laminate. Each collector pad is connected to a conductive lead (e.g., a printed circuit trace) that extends from each collector pad to the edge of the first insulator layer. A second insulator layer is positioned above the first insulator layer such that the collector pad(s) and their respective lead(s) are sandwiched between the two insulator layers. An adhesive is used to affix the second insulator to the first insulator and the collector pads. The collector pads are exposed to the plasma through apertures defined by the second insulator layer.
摘要翻译：用于测量半导体晶片处理系统内的等离子体特性的装置及其制造和使用方法。该装置包含第一绝缘体层，通过图案化和蚀刻铜层压体而形成一个或多个导电集电极焊盘。每个集电极焊盘连接到从每个集电极焊盘延伸到第一绝缘体层的边缘的导电引线（例如印刷电路迹线）。第二绝缘体层位于第一绝缘体层之上，使得集电极焊盘及其相应的引线夹在两个绝缘体层之间。使用粘合剂将第二绝缘体固定到第一绝缘体和集电板。集电极焊盘通过由第二绝缘体层限定的孔暴露于等离子体。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式