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1. 发明授权

US09996499B2 Scalable and programmable processor comprising multiple cooperating processor units 有权
公开(公告)号：US09996499B2
公开(公告)日：2018-06-12
申请号：US13248869
申请日：2011-09-29
申请人： Dusan Suvakovic , Adriaan J. de Lind van Wijngaarden , Man Fai Lau
发明人： Dusan Suvakovic , Adriaan J. de Lind van Wijngaarden , Man Fai Lau
IPC分类号： G06F15/78 , G06F9/38
CPC分类号： G06F15/7867 , G06F9/3897 , Y02D10/12 , Y02D10/13
摘要： A processor comprises a plurality of processor units arranged to operate concurrently and in cooperation with one another, and control logic configured to direct the operation of the processor units. At least a given one of the processor units comprises a memory, an arithmetic engine and a switch fabric. The switch fabric provides controllable connectivity between the memory, the arithmetic engine and input and output ports of the given processor unit, and has control inputs driven by corresponding outputs of the control logic. In an illustrative embodiment, the processor units may be configured to perform computations associated with a key equation solver in a Reed-Solomon (RS) decoder or other type of forward error correction (FEC) decoder.

2. 发明授权

US09459927B2 Central office based virtual personal computer 有权
标题翻译：中央办公室虚拟个人电脑
公开(公告)号：US09459927B2
公开(公告)日：2016-10-04
申请号：US12125315
申请日：2008-05-22
申请人： Martin D. Carroll , Hungkei Keith Chow , Ilija Hadzic , Ronald L. Sharp , Theodore Sizer, II , Dusan Suvakovic , Doutje T. Van Veen
发明人： Martin D. Carroll , Hungkei Keith Chow , Ilija Hadzic , Ronald L. Sharp , Theodore Sizer, II , Dusan Suvakovic , Doutje T. Van Veen
IPC分类号： G06F9/455 , G06F9/50 , G06F9/48
CPC分类号： G06F9/5077 , G06F9/4856
摘要： A virtual personal computer is implemented in a communication system comprising a plurality of central offices each of which communicates with a plurality of client devices over a corresponding access network. A given one of the central offices comprises at least one compute server and at least one storage server. The virtual personal computer is configured by allocating physical processing resources of the compute server and physical storage resources of the storage server to that virtual personal computer. User access is provided to the virtual personal computer via one of the client devices. The virtual personal computer can be dynamically reconfigured by altering the allocation of at least one of the physical processing resources and the physical storage resources to the given virtual personal computer responsive to particular applications selected by the user to run on the given virtual personal computer.
摘要翻译：在包括多个中心局的通信系统中实现虚拟个人计算机，每个中心局通过相应的接入网络与多个客户端设备进行通信。给定的一个中心局包括至少一个计算服务器和至少一个存储服务器。通过将计算服务器的物理处理资源和存储服务器的物理存储资源分配给该虚拟个人计算机来配置虚拟个人计算机。用户访问通过其中一个客户端设备提供给虚拟个人计算机。响应于用户选择的在给定的虚拟个人计算机上运行的特定应用，可以通过将物理处理资源和物理存储资源中的至少一个的分配改变到给定的虚拟个人计算机来动态地重新配置虚拟个人计算机。

3. 发明授权

US08959251B2 Implementation of switches in a communication network 有权
标题翻译：在通信网络中实现交换机
公开(公告)号：US08959251B2
公开(公告)日：2015-02-17
申请号：US12828443
申请日：2010-07-01
申请人： Dusan Suvakovic
发明人： Dusan Suvakovic
IPC分类号： G06F3/00 , H04Q11/00 , H04J3/04
CPC分类号： H04Q11/00 , H04J3/047
摘要： A routing device such as either a 1:N demultiplexer or N:1 multiplexer can provide a power dissipation proportional to log2(N) by augmenting a conventional data demultiplexer/multiplexer with additional control circuitry. The control circuit ensures that control signals that trigger configuration of individual demultiplexer/multiplexer elements are propagated only along a data transmission path. Logic components of the control circuitry enable the multiplexers to be self-configuring and to prevent multiplexers from switching to elements with empty data buffers.
摘要翻译：诸如1：N解复用器或N：1多路复用器之类的路由设备可以通过用附加的控制电路来增加常规的数据解复用器/多路复用器来提供与log2（N）成比例的功率消耗。控制电路确保触发各个解复用器/复用器元件的配置的控制信号仅沿着数据传输路径传播。控制电路的逻辑组件使多路复用器能够自配置，并防止多路复用器切换到具有空数据缓冲器的元件。

4. 发明申请

US20140126919A1 Method And Apparatus For Processing Bit-Interleaved Data Traffic In A Communication Network 有权
标题翻译：在通信网络中处理位交错数据流量的方法和装置
公开(公告)号：US20140126919A1
公开(公告)日：2014-05-08
申请号：US13853754
申请日：2013-03-29
申请人： Nagaraj Prasanth Anthapadmanabhan , Dusan Suvakovic , Hungkei Keith Chow , Doutje T. Van Veen
发明人： Nagaraj Prasanth Anthapadmanabhan , Dusan Suvakovic , Hungkei Keith Chow , Doutje T. Van Veen
IPC分类号： H04B10/66
CPC分类号： H04L25/03866 , H04L1/0071
摘要： A manner of processing bit-interleaved data traffic in a communication network. In the increasingly-common scenario where data traffic is bit interleaved and scrambled using a PRBS (pseudo-random binary sequence) before it is transmitted from a sender to a receiver, the receiver is configured to receive the transmitted bit stream and decimate it, that is, remove the bits of the bit stream that are allocated for the receiver, prior to descrambling. To accomplish this, the receiver employs an LFSR (linear feedback shift register) similar or identical to the one used by the sender to scramble the data. The LFSR is initialized by employing helper bits inserted by the sender or an initialization unit, and may employ other techniques for phase adjustment or state skipping depending on the nature of the transmitted bit stream.
摘要翻译：在通信网络中处理比特交织的数据业务的方式。在越来越常见的情况下，在从发送器发送到接收器之前，使用PRBS（伪随机二进制序列）将数据业务进行比特交织和加扰，接收器被配置为接收所发送的比特流并对其进行抽取，是在解扰之前去除分配给接收机的比特流的比特。为了实现这一点，接收机采用与发送方使用的LFSR（线性反馈移位寄存器）类似或相同的数据来加扰数据。通过使用由发送者或初始化单元插入的辅助位来初始化LFSR，并且可以根据发送的比特流的性质使用用于相位调整或状态跳过的其他技术。

5. 发明申请

US20130322885A1 DOWN-SAMPLING CLOCK AND DATA RECOVERY CIRCUIT HAVING SELECTABLE RATE AND PHASE OUTPUT AND METHOD OF OPERATION THEREOF 有权
标题翻译：具有可选择速率和相位输出的下采样时钟和数据恢复电路及其操作方法
公开(公告)号：US20130322885A1
公开(公告)日：2013-12-05
申请号：US13486552
申请日：2012-06-01
申请人： Hungkei Chow , Dusan Suvakovic , Christophe Van Praet , Guy Torfs , Xin Yin , Zhisheng Li
发明人： Hungkei Chow , Dusan Suvakovic , Christophe Van Praet , Guy Torfs , Xin Yin , Zhisheng Li
IPC分类号： H04L7/033
CPC分类号： H04L7/0337 , H03L7/0807 , H03L7/087 , H04L25/06 , Y02D50/10
摘要： A clock and data recovery (CDR) circuit, a method of recovering a clock and data from a received raw data stream and a BI-PON optical network transceiver (ONT) receiver front-end incorporating the CDR circuit. In one embodiment, the CDR circuit includes: (1) a line rate CDR circuit having a voltage controlled oscillator, the line rate CDR circuit configured to recover a raw data stream at a receiving line rate, (2) a fixed-rate down-sampler coupled to the line rate CDR circuit and configured to down-sample the raw data stream based on a fixed-rate and (3) a variable-rate down-sampler coupled to the fixed-rate down-sampler and configured further to down-sample the raw data sample based on a variable-rate.
摘要翻译：时钟和数据恢复（CDR）电路，一种从接收到的原始数据流中恢复时钟和数据的方法以及包含CDR电路的BI-PON光网络收发器（ONT）接收器前端的方法。在一个实施例中，CDR电路包括：（1）具有压控振荡器的线路速率CDR电路，所述线路速率CDR电路被配置为以接收线路速率恢复原始数据流，（2）固定速率下变频，采样器，其耦合到线路速率CDR电路并且被配置为基于固定速率对原始数据流进行下采样;以及（3）耦合到固定速率下采样器的可变速率下采样器，基于可变速率对原始数据采样进行采样。

6. 发明授权

US08086104B2 System, method and computer readable medium for providing dual rate transmission on a gigabit passive optical network 有权
标题翻译：用于在千兆无源光网络上提供双速率传输的系统，方法和计算机可读介质
公开(公告)号：US08086104B2
公开(公告)日：2011-12-27
申请号：US12070225
申请日：2008-02-15
申请人： Dusan Suvakovic
发明人： Dusan Suvakovic
IPC分类号： H04B10/00
CPC分类号： H04Q11/0067
摘要： In a dual rate gigabit passive optical network, an optical line termination (OLT) transmits a first rate (GPON) message frame interleaved with a second rate (NGPON) message frame. An unused ATM partition of the GPON message frame is provided with a header and payload portion of the NGPON message frame so that the message frame remains at a predetermined length required by the network.
摘要翻译：在双速千兆无源光网络中，光线路终端（OLT）发送与第二速率（NGPON）消息帧交织的第一速率（GPON）消息帧。 GPON消息帧的未使用的ATM分区被提供有NGPON消息帧的报头和有效载荷部分，使得消息帧保持在网络所需的预定长度。

7. 发明授权

US07242739B2 Method and apparatus for multiphase, fast-locking clock and data recovery 有权
标题翻译：用于多相，快速锁定时钟和数据恢复的方法和装置
公开(公告)号：US07242739B2
公开(公告)日：2007-07-10
申请号：US10460572
申请日：2003-06-12
申请人： Glenn M Boles , Alfred Earl Dunlop , Manyalibo Joseph Matthews , Dusan Suvakovic , Doutje T. Van Veen
发明人： Glenn M Boles , Alfred Earl Dunlop , Manyalibo Joseph Matthews , Dusan Suvakovic , Doutje T. Van Veen
IPC分类号： H03D3/24
CPC分类号： H04L7/0338 , H04L7/042
摘要： A method and apparatus for clock and data recovery that is advantageous in burst-mode systems is disclosed. This clock and data recovery method allows a) fast locking to a rapidly changed phase of the transmission clock, and b) stable tracking of a slowly changing phase of the transmission clock. Such fast locking minimizes the “guard band” between consecutive transmission bursts, while stable tracking provides reliable data tracking, resulting in the efficient use of bandwidth. A plurality of clock signals, is generated, each having a different phase. The phase of an input signal data stream is determined and a desired clock signal in the plurality that corresponds to the phase of the input data stream is selected and used to sample the input signal data stream.
摘要翻译：公开了一种在突发模式系统中有利的用于时钟和数据恢复的方法和装置。该时钟和数据恢复方法允许a）快速锁定到传输时钟的快速变化的相位，以及b）稳定跟踪传输时钟的缓慢变化的相位。这种快速锁定使连续传输突发之间的“保护带”最小化，而稳定跟踪提供可靠的数据跟踪，导致带宽的有效使用。产生多个时钟信号，每个具有不同的相位。确定输入信号数据流的相位，并且选择与输入数据流的相位相对应的多个中的期望时钟信号，并将其用于采样输入信号数据流。

8. 发明授权

US09621360B2 System and method for analyzing network power consumption 有权
公开(公告)号：US09621360B2
公开(公告)日：2017-04-11
申请号：US13011487
申请日：2011-01-21
申请人： George Endicott Rittenhouse , Gary Weldon Atkinson , Oliver Blume , Suresh Goyal , Daniel Charles Kilper , Steven Kenneth Korotky , Dusan Suvakovic
发明人： George Endicott Rittenhouse , Gary Weldon Atkinson , Oliver Blume , Suresh Goyal , Daniel Charles Kilper , Steven Kenneth Korotky , Dusan Suvakovic
IPC分类号： H04L12/26 , H04L12/28 , H04L12/12
CPC分类号： H04L12/12 , Y02D30/20 , Y02D50/40
摘要： A system and method for analyzing network power consumption is disclosed. The system and method for analyzing network power consumption includes the steps of specifying at least one service which will run on said network; defining a plurality of resources provisioned in the network, each having an associated power efficiency; associating a network path with the service; calculating a sum of the power efficiencies for the resources of the network path; and outputting the sum to a display device. The system and method for analyzing network power consumption is particularly useful for identifying power consumption efficiencies throughout a communication network.

9. 发明申请

US20160233884A1 LOW POWER LOW-DENSITY PARITY-CHECK DECODING 有权
标题翻译：低功率低密度奇偶校验解码
公开(公告)号：US20160233884A1
公开(公告)日：2016-08-11
申请号：US14615717
申请日：2015-02-06
申请人： Behnam Sedighi , Nagaraj Prasanth Anthapadmanabhan , Dusan Suvakovic
发明人： Behnam Sedighi , Nagaraj Prasanth Anthapadmanabhan , Dusan Suvakovic
IPC分类号： H03M13/11 , H03M13/00
CPC分类号： H03M13/112 , H03M13/1122 , H03M13/6502 , H03M13/6572 , H03M13/6575 , H03M13/6577
摘要： In general, a minimum determination capability, adapted for determining one or more minimum values from a set of values, is provided. The minimum determination capability may enable, for a set of values, determination of a first minimum value representing a smallest value of the set of values and a second minimum value representing an approximation of a next-smallest value of the set of values. The minimum determination capability may enable, for a set of values where each of the values is represented as a respective set of bits at a respective set of bit positions, determination of a minimum value of the set of values based on a set of bitwise comparisons performed for the respective bit positions of the values.
摘要翻译：通常，提供适于从一组值确定一个或多个最小值的最小确定能力。最小确定能力可以为一组值确定表示该组值的最小值的第一最小值，以及表示该组值的下一个最小值的近似值的第二最小值。对于一组值，最小确定能力可以使得其中每个值被表示为在相应位位置集合处的相应位组的值的集合，基于一组比特比较来确定该组值的最小值对于值的各个位位置执行。

10. 发明申请

US20120079236A1 SCALABLE AND PROGRAMMABLE PROCESSOR COMPRISING MULTIPLE COOPERATING PROCESSOR UNITS 有权
标题翻译：包含多个协同处理器单元的可扩展和可编程处理器
公开(公告)号：US20120079236A1
公开(公告)日：2012-03-29
申请号：US13248869
申请日：2011-09-29
申请人： Dusan Suvakovic , Adriaan J. de Lind van Wijngaarden , Man Fai Lau
发明人： Dusan Suvakovic , Adriaan J. de Lind van Wijngaarden , Man Fai Lau
IPC分类号： G06F9/312 , G06F15/76
CPC分类号： G06F15/7867 , G06F9/3897 , Y02D10/12 , Y02D10/13
摘要： A processor comprises a plurality of processor units arranged to operate concurrently and in cooperation with one another, and control logic configured to direct the operation of the processor units. At least a given one of the processor units comprises a memory, an arithmetic engine and a switch fabric. The switch fabric provides controllable connectivity between the memory, the arithmetic engine and input and output ports of the given processor unit, and has control inputs driven by corresponding outputs of the control logic. In an illustrative embodiment, the processor units may be configured to perform computations associated with a key equation solver in a Reed-Solomon (RS) decoder or other type of forward error correction (FEC) decoder.
摘要翻译：处理器包括多个处理器单元，其被布置为并行地并且彼此协作地操作，以及控制逻辑，其被配置为指导处理器单元的操作。至少一个处理器单元中的一个包括存储器，算术引擎和交换结构。交换结构提供了存储器，算术引擎和给定处理器单元的输入和输出端口之间的可控连接，并具有由控制逻辑的相应输出驱动的控制输入。在说明性实施例中，处理器单元可以被配置为执行与里德 - 所罗门（RS）解码器或其他类型的前向纠错（FEC）解码器中的密钥方程解算器相关联的计算。

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