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    • 5. 发明授权
    • Method and system of enhancing signal processing in a shared medium network
    • 在共享介质网络中增强信号处理的方法和系统
    • US09356854B2
    • 2016-05-31
    • US13838970
    • 2013-03-15
    • Echelon Corporation
    • Philip H. SutterlinGlen M. RileyWalter J. Downey
    • H04L12/26H04L12/413H04W74/08
    • H04W72/085H03M13/09H04L12/413H04L43/16H04W74/0841
    • A method implemented in a device is disclosed for networking through signals transmitted across a shared medium network. The method starts with monitoring for a first signal on a shared medium of the shared medium network. The first signal is processed after it is received and while the first signal is being processed, a set of one or more signals is received on the shared medium. Then a set of one or more amplitude increases is determined, where each amplitude increase is from an earlier received signal to a later received signal. The set of one or more amplitude increases is compared to a threshold value and at least partially in response to the comparison, the device discards one or more signals from the first signal and the set of one or more signals.
    • 公开了一种在设备中实现的方法,用于通过跨共享介质网络传输的信号进行组网。 该方法开始于监视共享介质网络的共享介质上的第一信号。 在接收到第一信号之后,在处理第一信号的同时,在共享介质上接收一组一个或多个信号。 然后确定一组或多个振幅增加,其中每个幅度增加是从较早接收的信号到稍后接收的信号。 将一个或多个振幅增加的集合与阈值进行比较,并且至少部分地响应于比较,设备从第一信号和一个或多个信号的集合中丢弃一个或多个信号。
    • 6. 发明申请
    • MULTI-PROTOCOL SERIAL NONVOLATILE MEMORY INTERFACE
    • 多协议串行非易失性存储器接口
    • US20150378959A1
    • 2015-12-31
    • US14319271
    • 2014-06-30
    • Echelon Corporation
    • Thomas Carleton Jones
    • G06F13/42G06F11/14G06F11/07G06F3/06G06F13/364
    • G06F13/4291G06F3/061G06F3/0661G06F3/0679G06F11/0757G06F11/1469G06F13/364G06F2201/84G06F2206/1014
    • An electronic device including a multi-protocol serial nonvolatile memory interface is disclosed. The interface includes: a first line operative to perform functions of a first chip select line when the interface operates as a SPI of the electronic device; a second line operative to perform functions of a second chip select line when the interface operates as the SPI of the electronic device; a third line operative to perform functions of a clock line when the interface operates as either the SPI or an I2C interface of the electronic device, and a fourth line configured to perform functions of a mast-out-slave-in (MOSI) line and a master-in-slave-out (MISO) line when the interface operates as the SPI of the electronic device, the fourth line further operative to perform functions of a serial data line when the interface operates as the I2C interface of the electronic device.
    • 公开了一种包括多协议串行非易失性存储器接口的电子设备。 所述接口包括:当所述接口作为所述电子设备的SPI操作时,操作用于执行第一芯片选择线的功能的第一线路; 当接口作为电子设备的SPI操作时,第二线路可操作以执行第二芯片选择线的功能; 当所述接口作为所述电子设备的SPI或I2C接口工作时,第三线路用于执行时钟线路的功能;以及第四线路,被配置为执行桅杆输出从属(MOSI)线路的功能,以及 当接口作为电子设备的SPI工作时,主从从(MISO)线路,当接口作为电子设备的I2C接口工作时,第四行进一步操作以执行串行数据线的功能。