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1. 发明授权

US06368970B1 Semiconductor configuration and corresponding production process 有权
标题翻译：半导体配置及相应的生产工艺
公开(公告)号：US06368970B1
公开(公告)日：2002-04-09
申请号：US09645238
申请日：2000-08-24
申请人： Ayad Abdul-Hak , Achim Gratz , Christoph Ludwig , Reinhold Rennekamp , Elard Stein Von Kamienski , Peter Wawer
发明人： Ayad Abdul-Hak , Achim Gratz , Christoph Ludwig , Reinhold Rennekamp , Elard Stein Von Kamienski , Peter Wawer
IPC分类号： H01L21302
CPC分类号： H01L21/76232 , H01L21/823481
摘要： A process for producing a semiconductor configuration includes the steps of providing a semiconductor substrate, providing a buffer oxide layer on the semiconductor substrate and providing a hard mask on the buffer oxide layer. An STI trench is etched by using the hard mask and a liner oxide layer is provided in the STI trench. The hard mask is removed to expose the buffer oxide layer and the buffer oxide layer is removed by an etching process. The buffer oxide layer is etched more rapidly than the liner oxide layer in the etching process. A gate oxide layer is provided on the semiconductor substrate. A semiconductor configuration is also provided.
摘要翻译：一种制造半导体结构的方法包括以下步骤：提供半导体衬底，在半导体衬底上提供缓冲氧化物层，并在缓冲氧化物层上提供硬掩模。通过使用硬掩模蚀刻STI沟槽，并且在STI沟槽中提供衬垫氧化物层。去除硬掩模以暴露缓冲氧化物层，并通过蚀刻工艺除去缓冲氧化物层。在蚀刻工艺中，缓冲氧化物层比衬垫氧化物层蚀刻得更快。在半导体衬底上设置栅氧化层。还提供半导体配置。

2. 发明授权

US07151697B2 Non-volatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US07151697B2
公开(公告)日：2006-12-19
申请号：US11000335
申请日：2004-11-30
申请人： Stephan Riedel , Elard Stein von Kamienski , Norbert Schulze
发明人： Stephan Riedel , Elard Stein von Kamienski , Norbert Schulze
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , G11C16/0466 , H01L27/1203
摘要： A non-volatile semiconductor memory includes a substrate having a substrate region, at least one word line, a plurality of non-volatile memory cells arranged in a plurality of sectors and further comprising first wells of a first doping type, electrically insulating elements and switching elements. Each sector includes a plurality of non-volatile memory cells commonly arranged in a respective first well. The at least one word line electrically connecting memory cells of a group of sectors among the plurality of sectors. The first wells are separated from the substrate region and from each other by means of the electrically insulating elements. Each first well is connected to a respective switching element and the semiconductor memory is constructed such that each first well is biasable to a predetermined potential by means of the respective switching element. Further, a method is provided for operating the above non-volatile semiconductor memory.
摘要翻译：非挥发性半导体存储器包括具有衬底区域，至少一个字线，布置在多个扇区中的多个非易失性存储单元的衬底，并且还包括第一掺杂类型的第一阱，电绝缘元件和开关元素。每个扇区包括通常布置在相应的第一阱中的多个非易失性存储器单元。所述至少一个字线电连接所述多个扇区中的一组扇区的存储单元。第一个阱通过电绝缘元件从衬底区域和彼此分离。每个第一阱连接到相应的开关元件，并且半导体存储器被构造成使得每个第一阱通过相应的开关元件可偏置到预定电位。此外，提供了用于操作上述非易失性半导体存储器的方法。

3. 发明授权

US07008849B2 Method for providing bitline contacts in a memory cell array and a memory cell array having bitline contacts 失效
标题翻译：用于在存储单元阵列中提供位线触点的方法和具有位线触点的存储单元阵列
公开(公告)号：US07008849B2
公开(公告)日：2006-03-07
申请号：US10724903
申请日：2003-12-01
申请人： Grit Schwalbe , Kae-Horng Wang , Klaus Feldner , Elard Stein Von Kamienski
发明人： Grit Schwalbe , Kae-Horng Wang , Klaus Feldner , Elard Stein Von Kamienski
IPC分类号： H01L21/8236
CPC分类号： H01L27/11568 , H01L21/76885 , H01L21/76897 , H01L27/112
摘要： A method for providing bitline contacts in a memory cell array includes a plurality of bitlines disposed in a first direction, the bitlines being covered by an isolating layer, a plurality of wordlines disposed in a second direction perpendicular to the first direction above the bitlines, and memory cells disposed at the points at which the bitlines and wordlines cross each other. According to a first aspect of the present invention, the isolating layer is removed from the bitlines at the portions that are not covered by the wordlines, whereas the areas between the bitlines remain unaffected. Alternatively, the isolating layer is removed from the whole cell array. Then, an electrical conductive material is provided on the exposed portions of the bitlines. The method is used to provide bitline contacts in a nitride read only memory (NROM™) chip.
摘要翻译：一种用于在存储单元阵列中提供位线触点的方法包括沿第一方向布置的多个位线，位线由绝缘层覆盖，多个字线沿垂直于位线上方的第一方向的第二方向布置，以及位于位线和字线彼此交叉的点处的存储单元。根据本发明的第一方面，在未被字线覆盖的部分处，从位线移除隔离层，而位线之间的区域保持不受影响。或者，从整个电池阵列中去除绝缘层。然后，在位线的露出部分上设置导电材料。该方法用于在氮化物只读存储器（NROM TM））芯片中提供位线触点。

4. 发明授权

US06645812B2 Method for fabricating a non-volatile semiconductor memory cell with a separate tunnel window 有权
公开(公告)号：US06645812B2
公开(公告)日：2003-11-11
申请号：US10033949
申请日：2001-12-28
申请人： Peter Wawer , Oliver Springmann , Konrad Wolf , Olaf Heitzsch , Kai Huckels , Reinhold Rennekamp , Mayk Röhrich , Elard Stein Von Kamienski , Christoph Kutter , Christoph Ludwig
发明人： Peter Wawer , Oliver Springmann , Konrad Wolf , Olaf Heitzsch , Kai Huckels , Reinhold Rennekamp , Mayk Röhrich , Elard Stein Von Kamienski , Christoph Kutter , Christoph Ludwig
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L29/7883
摘要： A method for producing a non-volatile semiconductor memory cell with a separate tunnel window cell includes the step of forming a tunnel zone in a late implantation step by performing a tunnel implantation with the aid of a tunnel window cell as a mask. The resulting memory cell has a small area requirement and a high number of program/clear cycles.

5. 发明授权

US07408222B2 Charge trapping device and method of producing the charge trapping device 有权
标题翻译：电荷俘获装置及电荷俘获装置的制造方法
公开(公告)号：US07408222B2
公开(公告)日：2008-08-05
申请号：US11390997
申请日：2006-03-27
申请人： Rainer Hagenbeck , Christoph Ludwig , Mark Isler , Elard Stein von Kamienski
发明人： Rainer Hagenbeck , Christoph Ludwig , Mark Isler , Elard Stein von Kamienski
IPC分类号： H01L29/76 , H01L21/331
CPC分类号： H01L29/0847 , H01L27/115 , H01L27/11568 , H01L29/66833 , H01L29/792
摘要： A charge-trapping device includes a field effect transistor, which has source and drain regions. The source and drain regions have a dopant concentration profile, which has a gradient each in a vertical and a lateral direction with respect to a surface of a semiconductor substrate. The gradient in the lateral direction towards a depletion region of the transistor is larger than the gradient in the vertical direction towards a well region.
摘要翻译：电荷捕获器件包括具有源极和漏极区域的场效应晶体管。源区和漏区具有掺杂剂浓度分布，其具有相对于半导体衬底的表面的垂直和横向方向的梯度。朝向晶体管的耗尽区域的横向的梯度大于朝向阱区域的垂直方向上的梯度。

6. 发明授权

US5859464A Optoelectronic diode and component containing same 失效
标题翻译：光电二极管和含有它的组件
公开(公告)号：US5859464A
公开(公告)日：1999-01-12
申请号：US732233
申请日：1996-09-26
申请人： Olaf Hollricher , Frank Ruders , Christoph Buchal , Hartmut Roskos , Jens Peter Hermanns , Elard Stein Von Kamienski , Klaus Rademacher
发明人： Olaf Hollricher , Frank Ruders , Christoph Buchal , Hartmut Roskos , Jens Peter Hermanns , Elard Stein Von Kamienski , Klaus Rademacher
IPC分类号： H01L31/108 , H01L31/00 , H01L27/095 , H01L29/47 , H01L31/0232
CPC分类号： H01L31/1085 , H01L31/108
摘要： An optoelectronic component has an Al.sub.2 O.sub.3 or Si substrate having a surface on which a buried CoSi.sub.2 layer is provided, a Si layer overlying the buried CoSi.sub.2 layer. A metal layer on a portion of this latter Si layer forms a diode between the metal layer, the underlying portion of the Si layer and the buried CoSi.sub.2 layer and a waveguide for a transparent portion of the metal layer delivers photon energy to the underlying portion of the Si layer.
摘要翻译： PCT No.PCT / DE95 / 00422 Sec。 371日期1996年9月26日 102（e）1996年9月26日PCT文件1995年3月28日PCT公布。公开号WO95 / 26572 日期1995年10月5日光电子部件具有Al 2 O 3或Si衬底，其具有设置有掩埋CoSi 2层的表面，覆盖掩埋CoSi 2层的Si层。后一Si层的一部分上的金属层在金属层，Si层的下面部分和掩埋的CoSi 2层之间形成二极管，并且用于金属层的透明部分的波导将光子能量传递到 Si层。

7. 发明授权

US06654281B2 Nonvolatile nor semiconductor memory device and method for programming the memory device 有权
公开(公告)号：US06654281B2
公开(公告)日：2003-11-25
申请号：US10177884
申请日：2002-06-20
申请人： Georg Georgakos , Kai Huckels , Jakob Kriz , Christoph Kutter , Andreas Liebelt , Christoph Ludwig , Elard Stein von Kamienski , Peter Wawer
发明人： Georg Georgakos , Kai Huckels , Jakob Kriz , Christoph Kutter , Andreas Liebelt , Christoph Ludwig , Elard Stein von Kamienski , Peter Wawer
IPC分类号： G11C1604
CPC分类号： H01L27/11519 , G11C16/0416 , H01L27/11521
摘要： A nonvolatile NOR semiconductor memory device and a method for programming the memory device are described. The memory device has a multiplicity of one-transistor memory cells disposed in a matrix form being driven both via word lines and via bit lines. In this case, each one-transistor memory cell has both a source line and a drain line, as a result of which selective driving of the respective drain and source regions is obtained. In this way, a leakage current in the semiconductor memory device can be optimally reduced with minimal space requirement.

8. 发明授权

US07755130B2 Minority carrier sink for a memory cell array comprising nonvolatile semiconductor memory cells 失效
标题翻译：用于包含非易失性半导体存储单元的存储单元阵列的少数载波宿
公开(公告)号：US07755130B2
公开(公告)日：2010-07-13
申请号：US11747037
申请日：2007-05-10
申请人： Elard Stein Von Kamienski
发明人： Elard Stein Von Kamienski
IPC分类号： H01L29/94
CPC分类号： H01L21/28282 , H01L27/115 , H01L27/11521 , H01L29/32 , H01L29/66833
摘要： A memory cell array of nonvolatile semiconductor memory cells is specified in which a minority carrier sink is formed within a semiconductor body in the region of the memory cell array, the minority carrier sink being arranged outside a space charge zone structure that forms in the semiconductor body during operation of the semiconductor memory cells, and the minority carrier sink having a shorter minority carrier lifetime in comparison with a semiconductor zone reaching as far as a surface of the semiconductor body.
摘要翻译：规定了非易失性半导体存储单元的存储单元阵列，其中在存储单元阵列的区域内在半导体本体内形成少数载流子阱，少数载流子排布置在形成于半导体本体中的空间电荷区结构之外在与半导体本体的表面一样远的半导体区域的情况下，半导体存储单元的工作期间和少数载流子阱具有较短的少数载流子寿命。

9. 发明申请

US20080277717A1 MINORITY CARRIER SINK FOR A MEMORY CELL ARRAY COMPRISING NONVOLATILE SEMICONDUCTOR MEMORY CELLS 失效
标题翻译：用于包含非易失性半导体存储器单元的存储器阵列的少量载体
公开(公告)号：US20080277717A1
公开(公告)日：2008-11-13
申请号：US11747037
申请日：2007-05-10
申请人： Elard Stein Von Kamienski
发明人： Elard Stein Von Kamienski
IPC分类号： H01L27/088
CPC分类号： H01L21/28282 , H01L27/115 , H01L27/11521 , H01L29/32 , H01L29/66833
摘要： A memory cell array of nonvolatile semiconductor memory cells is specified in which a minority carrier sink is formed within a semiconductor body in the region of the memory cell array, the minority carrier sink being arranged outside a space charge zone structure that forms in the semiconductor body during operation of the semiconductor memory cells, and the minority carrier sink having a shorter minority carrier lifetime in comparison with a semiconductor zone reaching as far as a surface of the semiconductor body.
摘要翻译：规定了非易失性半导体存储单元的存储单元阵列，其中在存储单元阵列的区域内在半导体本体内形成少数载流子阱，少数载流子排布置在形成于半导体本体中的空间电荷区结构之外在与半导体本体的表面一样远的半导体区域的情况下，半导体存储单元的工作期间和少数载流子阱具有较短的少数载流子寿命。

10. 发明授权

US07026220B1 Method for production of charge-trapping memory devices 失效
标题翻译：电荷俘获存储器件的制造方法
公开(公告)号：US07026220B1
公开(公告)日：2006-04-11
申请号：US11006484
申请日：2004-12-07
申请人： Georg Tempel , Elard Stein von Kamienski , Stephan Riedel , Veronika Polei , Roland Haberkern , Roman Knoefler
发明人： Georg Tempel , Elard Stein von Kamienski , Stephan Riedel , Veronika Polei , Roland Haberkern , Roman Knoefler
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L27/11568 , H01L27/115 , Y10S438/954
摘要： The method aims at improving the charge confinement of the memory layer at the edges facing the regions of buried bitlines. After the deposition of the memory layer between confinement layers and the implantation of dopants for bitlines and source/drain regions, an oxidation of semiconductor material to form upper bitline isolation regions takes place. By this method, additional oxide regions are produced at the edges of the memory layer in the same oxidation step. Either a silicon layer may be deposited and reduced to sidewall spacers, which are subsequently oxidized; or recesses are etched into the memory layer and subsequently filled with semiconductor oxide.
摘要翻译：该方法旨在改善面向掩埋位线区域的边缘处的存储层的电荷限制。在限制层之间的存储层沉积和用于位线和源/漏区的掺杂剂的注入之后，发生半导体材料的氧化以形成上位线隔离区。通过该方法，在相同的氧化步骤中在存储层的边缘产生附加的氧化物区域。可以将硅层沉积并还原成侧壁间隔物，其随后被氧化; 或凹槽蚀刻到存储层中，随后填充半导体氧化物。

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