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1. 发明授权

US11173274B2 Sleeper detection and configuration of sleep environments and learning methods to optimize sleep quality 有权
公开(公告)号：US11173274B2
公开(公告)日：2021-11-16
申请号：US16401092
申请日：2019-05-01
申请人： Ely Tsern , Jonathan Farringdon , John Tompane , Adam Hamel , Mark Handel
发明人： Ely Tsern , Jonathan Farringdon , John Tompane , Adam Hamel , Mark Handel
IPC分类号： A61M21/02 , A61B5/00 , A61B5/11 , A61M21/00
摘要： A bed includes environmental control components, which may be temperature control components and pressure adjustment components in some embodiments. The environmental control components may be configured to provide different sleep environments based on identity of sleepers using or expected to use the bed. A controller may determine a number of sleepers for the bed, identify the sleepers, and determine if there is an expectation of later arrival of sleeper in determining a configuration for the environmental control components in providing a sleep environment for the bed.

2. 发明授权

US08824224B2 Frequency-agile strobe window generation 有权
标题翻译：频敏捷频闪窗生成
公开(公告)号：US08824224B2
公开(公告)日：2014-09-02
申请号：US13545255
申请日：2012-07-10
申请人： Frederick A. Ware , Brian S. Leibowitz , Ely Tsern
发明人： Frederick A. Ware , Brian S. Leibowitz , Ely Tsern
IPC分类号： G11C19/00
CPC分类号： G11C29/023 , G06F13/1689 , G11C7/1066 , G11C29/022 , G11C29/028 , H03K5/135
摘要： The disclosed embodiments relate to components of a memory system that support frequency-agile strobe enable window generation during read accesses. In specific embodiments, this memory system contains a memory controller which includes a timing circuit to synchronize a timing-enable signal with a timing signal returned from a read path, wherein the timing signal includes a delay from the read path. In some embodiments, the timing circuit further comprises two calibration loops. The first calibration loop tracks the timing-enable signal with respect to a cycle-dependent delay in the delay, wherein the cycle-dependent delay depends on a frequency of the strobe signal. The second calibration loop tracks the timing-enable signal with respect to a cycle-independent delay in the delay, wherein the cycle-independent delay does not depend on the frequency of the strobe signal. In some embodiments, the first calibration loop and the second calibration loop are cascaded.
摘要翻译：所公开的实施例涉及在读取访问期间支持频率敏捷选通使能窗口生成的存储器系统的组件。在具体实施例中，该存储器系统包括存储器控制器，其包括定时电路，以使定时使能信号与从读取路径返回的定时信号同步，其中定时信号包括来自读取路径的延迟。在一些实施例中，定时电路还包括两个校准回路。第一校准环路相对于延迟中的与周期相关的延迟跟踪定时使能信号，其中周期相关延迟取决于选通信号的频率。第二校准环路相对于延迟中的与周期无关的延迟来跟踪定时使能信号，其中周期无关延迟不依赖于选通信号的频率。在一些实施例中，级联第一校准回路和第二校准回路。

3. 发明授权

US08677285B2 User interface of a small touch sensitive display for an electronic data and communication device 有权
标题翻译：用于电子数据和通信设备的小型触敏显示器的用户界面
公开(公告)号：US08677285B2
公开(公告)日：2014-03-18
申请号：US12360030
申请日：2009-01-26
申请人： Ely Tsern , Dave Mooring
发明人： Ely Tsern , Dave Mooring
IPC分类号： G06F3/14 , G06F3/033 , G06F3/01
CPC分类号： G04G21/08 , G06F1/163 , G06F3/04883 , G06F2203/04808
摘要： A method and apparatus for receiving an input by a user on an interactive touchscreen display based, electronic data and communication device, the input comprising a contact gesture, which further comprises touchscreen single or multiple simultaneous contacts. The contact gestures are classified as primary, secondary, tertiary, universal and non-universal contact gestures. The method further includes performing an operation or entering an operational mode based on the user input.
摘要翻译：一种用于在基于交互式触摸屏显示器的电子数据和通信设备上接收用户的输入的方法和装置，所述输入包括接触手势，其还包括触摸屏单个或多个同时联系。接触手势被分为主要，次要，第三，通用和非通用接触手势。该方法还包括基于用户输入执行操作或进入操作模式。

4. 发明授权

US07685364B2 Memory system topologies including a buffer device and an integrated circuit memory device 有权
标题翻译：存储器系统拓扑，包括缓冲器和集成电路存储器件
公开(公告)号：US07685364B2
公开(公告)日：2010-03-23
申请号：US12424442
申请日：2009-04-15
申请人： Ian Shaeffer , Ely Tsern , Craig Hampel
发明人： Ian Shaeffer , Ely Tsern , Craig Hampel
IPC分类号： G06F12/00
CPC分类号： G11C11/4093 , G06F13/16 , G06F13/4027 , G06F13/4068 , G11C5/025 , G11C5/04 , G11C5/06 , G11C7/1006 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4096 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/32145 , H01L2224/48227 , H01L2224/73265 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.
摘要翻译：除了其它实施例之外，系统包括集成电路缓冲器件（可耦合到主器件，例如存储器控制器）与多个集成电路存储器件之间的拓扑（数据和/或控制/地址信息）。例如，可以响应于从集成电路缓冲器装置提供的控制/地址信息，在多个集成电路存储器件和集成电路缓冲器件之间使用单独的分段（或点到点链路）信号路径提供数据，所述多个集成电路缓冲器件使用单个飞越（或总线）信号路径。集成电路缓冲器件实现了多个集成电路存储器件的可配置的有效存储器组织。由集成电路缓冲器件表示为存储器控制器的存储器组织可以不同于后面或耦合到集成电路缓冲器件的实际存储器组织。缓冲器设备将期望特定内存组织的内存控制器和实际内存组织之间传输的数据进行分段并合并。

5. 发明授权

US07454555B2 Apparatus and method including a memory device having multiple sets of memory banks with duplicated data emulating a fast access time, fixed latency memory device 失效
标题翻译：装置和方法包括具有多组存储器组的存储器件，具有模拟快速存取时间的复制数据，固定延迟存储器件
公开(公告)号：US07454555B2
公开(公告)日：2008-11-18
申请号：US10865398
申请日：2004-06-10
申请人： Frederick A. Ware , Ely Tsern , Steven Woo , Richard E. Perego
发明人： Frederick A. Ware , Ely Tsern , Steven Woo , Richard E. Perego
IPC分类号： G06F12/00
CPC分类号： G11C11/413 , G11C7/1006 , G11C7/1039 , G11C7/1045 , G11C7/22 , G11C8/12
摘要： An apparatus includes two multi-bank memory devices for storing duplicate data in each memory bank in an embodiment of the invention. The two memory devices are able to replace a more expensive fast-cycle, fixed latency single memory device. In an embodiment of the invention, a memory controller includes controller logic and a plurality of write buffers for interleaving write transactions to each memory bank in the two memory devices. A memory controller also includes tag memory for identifying valid data in the memory banks. In another embodiment of the invention, a game console includes the apparatus and executes game software that requires fixed latency in a mode of operation. In yet another embodiment of the invention, each memory device is coupled to respective write channels. Write data is simultaneously written to two memory banks in respective sets of memory banks in a memory device in an embodiment of the present invention. In an alternate embodiment of the present invention, an apparatus includes four memory devices for storing duplicate data with each memory device having a set of memory banks. The four memory devices are coupled to a controller by four respective write channels.
摘要翻译：在本发明的实施例中，一种装置包括用于在每个存储体中存储重复数据的两个多存储体存储器件。两个存储器件能够替代更昂贵的快速循环，固定延迟单个存储器件。在本发明的实施例中，存储器控制器包括控制器逻辑和用于将写入事务交织到两个存储器件中的每个存储体的多个写入缓冲器。存储器控制器还包括用于识别存储体中的有效数据的标签存储器。在本发明的另一个实施例中，游戏机包括该装置并执行在操作模式中需要固定等待时间的游戏软件。在本发明的另一个实施例中，每个存储器件耦合到相应的写入通道。在本发明的一个实施例中，写入数据被同时写入存储器装置中相应存储体组中的两个存储体。在本发明的替代实施例中，一种装置包括四个用于存储与具有一组存储器组的每个存储器件重复数据的存储器件。四个存储器件通过四个相应的写通道耦合到控制器。

6. 发明授权

US07404032B2 Configurable width buffered module having switch elements 失效
标题翻译：可配置宽度缓冲模块，具有开关元件
公开(公告)号：US07404032B2
公开(公告)日：2008-07-22
申请号：US10889852
申请日：2004-07-13
申请人： Fred Ware , Richard Perego , Ely Tsern
发明人： Fred Ware , Richard Perego , Ely Tsern
IPC分类号： G06F12/00
CPC分类号： G06F13/1684 , G11C5/04 , G11C7/10 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2029/1806 , H05K1/181
摘要： A memory system architecture/interconnect topology includes a configurable width buffered memory module having a configurable width buffer device with at least one switch element. A buffer device, such as a configurable width buffer device, is positioned between or with at least one integrated circuit memory device positioned on a substrate surface of a memory module, such as a DIMM. A switch element is positioned on or off a memory module and includes two transistors in embodiments of the invention. One or more switch elements are coupled to one or more channels to allow for upgrades of memory modules in a memory system. An asymmetrical switch topology allows for increasing the number of memory modules to more than two memory modules without adding switch elements serially on each channel. Switch elements allow for increasing the number of ranks of memory modules in a system, while also achieving many of the benefits associated with point-to-point topology.
摘要翻译：存储器系统架构/互连拓扑包括具有可配置宽度缓冲器件的可配置宽度缓冲存储器模块，其具有至少一个开关元件。诸如可配置的宽度缓冲器装置之类的缓冲装置被定位在位于诸如DIMM之类的存储器模块的衬底表面上的至少一个集成电路存储器件之间或之间。开关元件位于或离开存储器模块，并且在本发明的实施例中包括两个晶体管。一个或多个开关元件耦合到一个或多个通道以允许存储器系统中的存储器模块的升级。不对称开关拓扑允许将多个存储器模块增加到两个以上的存储器模块，而不是在每个通道上串行地添加开关元件。交换机元件允许增加系统中内存模块的数量，同时也可以实现与点对点拓扑相关的许多优点。

7. 发明申请

US20080080261A1 MEMORY SYSTEM TOPOLOGIES INCLUDING A BUFFER DEVICE AND AN INTEGRATED CIRCUIT MEMORY DEVICE 有权
标题翻译：包括缓冲器器件和集成电路存储器件的存储器系统拓扑
公开(公告)号：US20080080261A1
公开(公告)日：2008-04-03
申请号：US11697572
申请日：2007-04-06
申请人： Ian Shaeffer , Ely Tsern , Craig Hampel
发明人： Ian Shaeffer , Ely Tsern , Craig Hampel
IPC分类号： G11C7/10
CPC分类号： G11C11/4093 , G06F13/16 , G06F13/4027 , G06F13/4068 , G11C5/025 , G11C5/04 , G11C5/06 , G11C7/1006 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4091 , G11C11/4094 , G11C11/4096 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/32145 , H01L2224/48227 , H01L2224/73265 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.
摘要翻译：除了其它实施例之外，系统包括集成电路缓冲器件（可耦合到主器件，例如存储器控制器）与多个集成电路存储器件之间的拓扑（数据和/或控制/地址信息）。例如，可以响应于从集成电路缓冲器装置提供的控制/地址信息，在多个集成电路存储器件和集成电路缓冲器件之间使用单独的分段（或点到点链路）信号路径提供数据，所述多个集成电路缓冲器件使用单个飞越（或总线）信号路径。集成电路缓冲器件实现了多个集成电路存储器件的可配置的有效存储器组织。由集成电路缓冲器件表示为存储器控制器的存储器组织可以不同于后面或耦合到集成电路缓冲器件的实际存储器组织。缓冲器设备将期望特定内存组织的内存控制器和实际内存组织之间传输的数据进行分段并合并。

8. 发明授权

US07320047B2 System having a controller device, a buffer device and a plurality of memory devices 失效
标题翻译：具有控制器装置，缓冲装置和多个存储装置的系统
公开(公告)号：US07320047B2
公开(公告)日：2008-01-15
申请号：US11136995
申请日：2005-05-25
申请人： Richard E. Perego , Stefanos Sidiropoulos , Ely Tsern
发明人： Richard E. Perego , Stefanos Sidiropoulos , Ely Tsern
IPC分类号： G06F12/00
CPC分类号： G11C29/028 , G06F13/1673 , G06F13/1684 , G11C5/04 , G11C7/10 , G11C29/02 , G11C29/50012
摘要： A system comprises a controller device, an integrated circuit buffer device and a first and second memory device. A first plurality of signal lines is coupled to the controller device. A second plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The second plurality of signal lines carries first address information from the integrated circuit buffer device to the first memory device. A third plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device. The third plurality of signal lines carries first control information from the integrated circuit buffer device to the first memory device. A first signal line is coupled to the first memory device and the integrated circuit buffer device. The first signal line carries a first signal from the integrated circuit buffer device to the first memory device. The first signal synchronizes communication of the first control information from the integrated circuit buffer device to the first memory device.
摘要翻译：一种系统包括控制器装置，集成电路缓冲装置以及第一和第二存储装置。第一多个信号线耦合到控制器设备。第二多个信号线耦合到第一存储器件和集成电路缓冲器件。第二多个信号线将第一地址信息从集成电路缓冲器装置传送到第一存储器件。第三组信号线耦合到第一存储器件和集成电路缓冲器件。第三多个信号线将第一控制信息从集成电路缓冲器装置传送到第一存储器件。第一信号线耦合到第一存储器件和集成电路缓冲器件。第一信号线将来自集成电路缓冲器件的第一信号传送到第一存储器件。第一信号使来自集成电路缓冲器的第一控制信息与第一存储器件的通信同步。

9. 发明申请

US20070220188A1 Expandable Slave Device System with Buffered Subsystems 有权
标题翻译：具有缓冲子系统的可扩展从设备系统
公开(公告)号：US20070220188A1
公开(公告)日：2007-09-20
申请号：US11752242
申请日：2007-05-22
申请人： Bruno Garlepp , Richard Barth , Kevin Donnelly , Ely Tsern , Craig Hampel , Jeffrey Mitchell , James Gasbarro , Billy Garrett , Fredrick Ware , Donald Perino
发明人： Bruno Garlepp , Richard Barth , Kevin Donnelly , Ely Tsern , Craig Hampel , Jeffrey Mitchell , James Gasbarro , Billy Garrett , Fredrick Ware , Donald Perino
IPC分类号： G06F13/14
CPC分类号： G06F13/4072 , G06F13/4086 , G06F13/4243
摘要： A system includes a first bus, a master device coupled to the first bus, and one or more subsystems coupled to the first bus. A respective subsystem includes a second bus, one or more slave devices coupled to the second bus, a write buffer to receive incoming signals from the master device via the first bus and to transmit signals to the one or more slave devices via the second bus in response to the incoming signals, and a read buffer to receive outgoing signals from the one or more slave devices via the second bus and to transmit signals to the master device via the first bus in response to the outgoing signals.
摘要翻译：系统包括第一总线，耦合到第一总线的主设备和耦合到第一总线的一个或多个子系统。相应的子系统包括第二总线，耦合到第二总线的一个或多个从设备，写入缓冲器，用于经由第一总线接收来自主设备的输入信号，以及经由第二总线将信号发送到一个或多个从设备响应于输入信号，以及读缓冲器，用于经由第二总线接收来自一个或多个从设备的输出信号，并响应于输出信号经由第一总线向主设备发送信号。

10. 发明申请

US20070146038A1 Clock distribution network supporting low-power mode 有权
标题翻译：时钟分配网络支持低功耗模式
公开(公告)号：US20070146038A1
公开(公告)日：2007-06-28
申请号：US11318290
申请日：2005-12-22
申请人： Carl Werner , Ely Tsern
发明人： Carl Werner , Ely Tsern
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： A clock distribution network locks a local clock signal to a reference clock signal using a first feedback loop associated with a synchronization circuit (e.g., a PLL or a DLL). The local clock signal can then be selectively distributed to a plurality of clock destination nodes via a clock network. Clock distribution may be disabled as needed to save power. The first feedback loop is active irrespective of whether clock distribution is enabled. The delay through the clock network may drift due to temperature and supply-voltage fluctuations, which introduces phase errors in the distributed clock signals. A second feedback loop is activated when clock distribution is enabled to compensate for this drift.
摘要翻译：时钟分配网络使用与同步电路（例如，PLL或DLL）相关联的第一反馈回路将本地时钟信号锁定到参考时钟信号。然后可以经由时钟网络选择性地将本地时钟信号分配给多个时钟目的地节点。可根据需要禁用时钟分配以节省电量。无论时钟分配是否启用，第一个反馈回路都处于活动状态。通过时钟网络的延迟可能由于温度和电源电压波动而漂移，这引起了分布式时钟信号中的相位误差。当启用时钟分配来补偿此漂移时，第二个反馈环路被激活。

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