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1. 发明申请

US20120303303A1 CORRECTION FOR STRESS INDUCED LEAKAGE CURRENT IN DIELECTRIC RELIABILITY EVALUATIONS 有权
标题翻译：电介质可靠性评估中应力诱导漏电流的校正
公开(公告)号：US20120303303A1
公开(公告)日：2012-11-29
申请号：US13117819
申请日：2011-05-27
申请人： Steven W. Mittl , Ernest Y. Wu
发明人： Steven W. Mittl , Ernest Y. Wu
IPC分类号： G06F19/00
CPC分类号： G01R31/12 , G01R31/26 , G01R31/2621 , G01R31/2642 , G06F19/00
摘要： Methods, apparatus, and computer program products for evaluating current transients measured during an electrical stress evaluation of a dielectric layer in a semiconductor device. Measured current transients are fit to an equation representing a time dependence for stress induced leakage currents. The measured current transients are corrected based upon stress currents computed from the equation to define corrected current transients.
摘要翻译：用于评估在半导体器件中的电介质层的电应力评估期间测量的电流瞬变的方法，装置和计算机程序产品。测量的电流瞬变适合于表示应力诱发漏电流的时间依赖性的方程式。测量的电流瞬变根据从等式计算的应力电流进行校正，以定义校正的电流瞬变。

2. 发明申请

US20120187974A1 Dual Stage Voltage Ramp Stress Test for Gate Dielectrics 审中-公开
标题翻译：栅极电介质的双级电压斜坡应力测试
公开(公告)号：US20120187974A1
公开(公告)日：2012-07-26
申请号：US13010081
申请日：2011-01-20
申请人： David G. Brochu, JR. , Roger A. Dufresne , Charles B. LaRow , Travis S. Merrill , Nilufa Rahim , Ernest Y. Wu
发明人： David G. Brochu, JR. , Roger A. Dufresne , Charles B. LaRow , Travis S. Merrill , Nilufa Rahim , Ernest Y. Wu
IPC分类号： G01R31/26
CPC分类号： G01R31/2623
摘要： A testing system for testing the integrity of a gate dielectric includes a testing apparatus, the testing apparatus including a test probe configured to contact and provide a voltage across the gate dielectric and to measure a current passing through the gate dielectric. The testing system also includes a computing device coupled to the testing apparatus an causing the testing apparatus to apply a constant voltage as part of a first test to the gate dielectric through the test probe until a first predetermined current is measured passing through the gate dielectric and to apply an increasing voltage to the gate dielectric after the first predetermined current is measured.
摘要翻译：用于测试栅极电介质的完整性的测试系统包括测试装置，测试装置包括被配置成接触并提供横跨栅极电介质的电压并测量通过栅极电介质的电流的测试探针。测试系统还包括耦合到测试装置的计算设备，使得测试设备通过测试探针将恒定电压作为第一测试的一部分施加到栅极电介质，直到通过栅极电介质测量第一预定电流，并且在测量第一预定电流之后，向栅极电介质施加增加的电压。

3. 发明授权

US07298161B2 Circuitry and methodology to establish correlation between gate dielectric test site reliability and product gate reliability 失效
标题翻译：电路和方法建立栅介质测试点可靠性与产品门可靠性之间的相关性
公开(公告)号：US07298161B2
公开(公告)日：2007-11-20
申请号：US11088953
申请日：2005-03-24
申请人： Kerry Bernstein , Ronald J. Bolam , Edward J. Nowak , Alvin W. Strong , Jody J. Van Horn , Ernest Y. Wu
发明人： Kerry Bernstein , Ronald J. Bolam , Edward J. Nowak , Alvin W. Strong , Jody J. Van Horn , Ernest Y. Wu
IPC分类号： G01R31/26
CPC分类号： G01R31/2855
摘要： A method and system for predicting gate reliability. The method comprises the steps of stressing a gate dielectric test site to obtain gate dielectric test site data and using the test site data to predict gate reliability. Preferably, the test structure and the product structure are integrated in such a manner that a test site occupies some of the product area and the product itself occupies the remainder of the product area. A preferred methodology, more specifically, is as follows: (1) Test structures at start both in parallel stress mode and in ring oscillator or “product” mode; (2) Analyze the breakdown data as per the present state of the art for each of the areas based on the parallel stress mode; (3) Combine the above breakdown distributions using the area scaling to improve the confidence bounds of the Weibull slope of the cumulative distribution function; (4) Test the ring oscillators in the product mode to determine how many of the stress fails are also product fails as defined by an operational degradation; (5) Subdivide the failures to determine the relationship between the first fail, and the second fail, and the nth fail; (6) Investigate which stress fail, if not the first stress fail, is more likely to cause a product fail as defined by operational degradation; and (7) Based on the subdivision in step 5 and the results in step 6, make projection based on that fail which is most likely to cause fail. The methodology as outlined above bridges between dielectric stress fails and product degradation both in the case of each stress fail causing a product degradation, as well as in the case where more than one stress fail occurs before any product degradation occurs. And this relationship can be quantified.
摘要翻译：一种用于预测门可靠性的方法和系统。该方法包括以下步骤：施加栅极电介质测试点以获得栅极介电测试点数据，并使用测试点数据来预测栅极的可靠性。优选地，测试结构和产品结构以这样的方式集成，使得测试位置占据产品区域中的一些，并且产品本身占据产品区域的其余部分。更具体地说，优选的方法如下：（1）并联应力模式和环形振荡器或“产品”模式下的测试结构; （2）根据平行应力模式分析每个区域的现有技术状况; （3）使用面积缩放结合上述分解分布，以提高累积分布函数的威布尔斜率的置信范围; （4）在产品模式下测试环形振荡器，以确定应力失效的数量是否也是由操作退化定义的产品故障; （5）细分失败，确定第一个失败与第二个失败之间的关系，第n个失败; （6）调查哪些压力失败，如果不是第一次压力失败，更有可能导致产品按作业退化所定义的失效; 和（7）基于步骤5中的细分和步骤6中的结果，基于最可能导致失败的失败进行投影。如上所述的方法在介电应力失效和产物退化两者之间，在每个应力失效导致产物降解的情况下，以及在任何产物降解发生之前发生多于一个应力失效的情况下。这种关系可以量化。

4. 发明授权

US08352900B1 Analytic experimental estimator for impact of voltage-overshoot of voltage waveform on dielectric failure/breakdown 有权
标题翻译：电压波形电压过冲对介质故障/击穿的影响的分析实验估计器
公开(公告)号：US08352900B1
公开(公告)日：2013-01-08
申请号：US13356681
申请日：2012-01-24
申请人： Ernest Y. Wu
发明人： Ernest Y. Wu
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method tests integrated circuit devices to measure a voltage overshoot condition. The method determines an overshoot time proportion. The overshoot time proportion is the amount of time the voltage overshoot condition occurs relative to the amount of time the normal operating condition occurs during a full useful operating lifetime of the integrated circuit devices. The method also determines an overshoot failure proportion. The overshoot failure proportion comprises the amount of dielectric failures that occur during the voltage overshoot condition relative to the amount of dielectric failures that occur during the normal operating condition. The method calculates an allowed overshoot voltage based on the overshoot time proportion and the overshoot failure proportion. The method additionally calculates an average overshoot voltage of a voltage waveform and compares the average overshoot voltage to the allowed overshoot voltage to identify if the average overshoot voltage exceeds the allowed overshoot voltage.
摘要翻译：一种测试集成电路器件以测量电压过冲条件的方法。该方法确定过冲时间比例。过冲时间比例是相对于在集成电路器件的完全有用工作寿命期间发生正常工作状态的时间量，发生电压过冲状态的时间量。该方法还确定过冲故障比例。过冲故障比例包括在电压过冲状态期间相对于在正常工作状态期间发生的电介质故障的量发生的电介质故障的量。该方法基于过冲时间比例和过冲故障比例计算允许的过冲电压。该方法另外计算电压波形的平均过冲电压，并将平均过冲电压与允许的过冲电压进行比较，以确定平均过冲电压是否超过允许的过冲电压。

5. 发明申请

US20090006014A1 Non-Destructive Electrical Characterization Macro and Methodology for In-Line Interconnect Spacing Monitoring 审中-公开
标题翻译：用于在线互连间隔监测的非破坏性电气特性宏观和方法
公开(公告)号：US20090006014A1
公开(公告)日：2009-01-01
申请号：US11769265
申请日：2007-06-27
申请人： Kaushik Chanda , Fen Chen , Paul S. McLaughlin , Ernest Y. Wu
发明人： Kaushik Chanda , Fen Chen , Paul S. McLaughlin , Ernest Y. Wu
IPC分类号： G01R27/26 , G01B21/28
CPC分类号： H01L22/34 , H01L22/12
摘要： A method for determining a line-to-line spacing of a device. The method includes experimentally determining a slope kCA, experimentally determining a slope kSE and determining a line-to-line spacing of a device from the slope kCA and the slope kSE. A structure for performing the method includes a non-destructive line-to-line spacing characterization macro.
摘要翻译：一种用于确定设备的行间距的方法。该方法包括实验地确定斜率kCA，通过实验确定斜率kSE并且从斜率kCA和斜率kSE确定装置的线间距离。用于执行该方法的结构包括非破坏性的线间距表征宏。

6. 发明授权

US06750530B1 Semiconductor antifuse with heating element 失效
标题翻译：半导体反熔丝加热元件
公开(公告)号：US06750530B1
公开(公告)日：2004-06-15
申请号：US10250093
申请日：2003-06-03
申请人： William A. Klaasen , Alvin W. Strong , Ernest Y. Wu
发明人： William A. Klaasen , Alvin W. Strong , Ernest Y. Wu
IPC分类号： H01L2900
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A programmable device including: an antifuse; a resistive heating element having a substantially temperature to power response, the resistive heating element adjacent to but not in contact with the antifuse; and means for passing an electric current through the resistive heating element in order to generate heat to raise the temperature of the antifuse sufficiently high enough to decrease a programming voltage of the antifuse, a time the programming voltage is applied to the antifuse or both the programming voltage of the antifuse and the time the programming voltage is applied to the antifuse.
摘要翻译：一种可编程装置，包括：反熔丝; 电阻加热元件具有基本的温度对功率响应，电阻加热元件邻近但不与反熔丝接触; 以及用于使电流通过电阻加热元件以产生热量以使反熔丝的温度足够高以足以降低反熔丝的编程电压，编程电压施加到反熔丝或编程的时间的装置反熔丝的电压和编程电压施加到反熔丝的时间。

7. 发明授权

US06891359B2 Circuitry and methodology to establish correlation between gate dielectric test site reliability and product gate reliability 失效
标题翻译：电路和方法建立栅介质测试点可靠性与产品门可靠性之间的相关性
公开(公告)号：US06891359B2
公开(公告)日：2005-05-10
申请号：US10248506
申请日：2003-01-24
申请人： Kerry Bernstein , Ronald J. Bolam , Edward J. Nowak , Alvin W. Strong , Jody J. Van Horn , Ernest Y. Wu
发明人： Kerry Bernstein , Ronald J. Bolam , Edward J. Nowak , Alvin W. Strong , Jody J. Van Horn , Ernest Y. Wu
IPC分类号： G01N27/00 , G01R27/00 , G01R31/02 , G01R31/28
CPC分类号： G01R31/2855
摘要： A method and system for predicting gate reliability. The method comprises the steps of stressing a gate dielectric test site to obtain gate dielectric test site data and using the test site data to predict gate reliability. Preferably, the test structure and the product structure are integrated in such a manner that a test site occupies some of the product area and the product itself occupies the remainder of the product area. A preferred methodology, more specifically, is as follows: (1) Test structures at start both in parallel stress mode and in ring oscillator or “product” mode; (2) Analyze the breakdown data as per the present state of the art for each of the areas based on the parallel stress mode; (3) Combine the above breakdown distributions using the area scaling to improve the confidence bounds of the Weibull slope of the cumulative distribution function; (4) Test the ring oscillators in the product mode to determine how many of the stress fails are also product fails as defined by an operational degradation; (5) Subdivide the failures to determine the relationship between the first fail, and the second fail, and the nth fail; (6) Investigate which stress fail, if not the first stress fail, is more likely to cause a product fail as defined by operational degradation; and (7) Based on the subdivision in step 5 and the results in step 6, make projection based on that fail which is most likely to cause fail. The methodology as outlined above bridges between dielectric stress fails and product degradation both in the case of each stress fail causing a product degradation, as well as in the case where more than one stress fail occurs before any product degradation occurs. And this relationship can be quantified.
摘要翻译：一种用于预测门可靠性的方法和系统。该方法包括以下步骤：施加栅极电介质测试点以获得栅极介电测试点数据，并使用测试点数据来预测栅极的可靠性。优选地，测试结构和产品结构以这样的方式集成，使得测试位置占据产品区域中的一些，并且产品本身占据产品区域的其余部分。更具体地说，优选的方法如下：（1）并联应力模式和环形振荡器或“产品”模式下的测试结构; （2）根据平行应力模式分析每个区域的现有技术状况; （3）使用面积缩放结合上述分解分布，以提高累积分布函数的威布尔斜率的置信范围; （4）在产品模式下测试环形振荡器，以确定应力失效的数量是否也是由操作退化定义的产品故障; （5）细分故障，确定第一个失败和第二个失败之间的关系，并且n ^{th 失败; （6）调查哪些压力失败，如果不是第一次压力失败，更有可能导致产品按作业退化所定义的失效; 和（7）基于步骤5中的细分和步骤6中的结果，基于最可能导致失败的失败进行投影。如上所述的方法在介电应力失效和产物退化两者之间，在每个应力失效导致产物降解的情况下，以及在任何产物降解发生之前发生多于一个应力失效的情况下。这种关系可以量化。}

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