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1. 发明授权

US08455985B2 Integrated circuit devices having selectively strengthened composite interlayer insulation layers and methods of fabricating the same 有权
标题翻译：具有选择性强化复合层间绝缘层的集成电路器件及其制造方法
公开(公告)号：US08455985B2
公开(公告)日：2013-06-04
申请号：US13019520
申请日：2011-02-02
申请人： Kyu-hee Han , Sang-hoon Ahn , Eunkee Hong
发明人： Kyu-hee Han , Sang-hoon Ahn , Eunkee Hong
IPC分类号： H01L29/00
CPC分类号： H01L23/562 , H01L21/02126 , H01L21/02274 , H01L21/76801 , H01L21/76825 , H01L23/5258 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L24/04 , H01L24/05 , H01L24/16 , H01L24/48 , H01L24/85 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05557 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/16145 , H01L2224/16245 , H01L2224/48137 , H01L2224/48145 , H01L2224/48245 , H01L2224/48247 , H01L2224/48463 , H01L2224/85205 , H01L2924/00014 , H01L2924/0002 , H01L2924/01019 , H01L2924/14 , H01L2224/05552 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： An integrated circuit device includes a plurality of stacked circuit layers, at least one of the plurality of circuit layers including a composite interlayer insulation layer including laterally adjacent first and second insulating material regions having different mechanical strengths and dielectric properties and a plurality of circuit components disposed in the composite interlayer insulation layer. The first insulating material region may have a lower dielectric constant and a lower mechanical strength than the second insulating material region such that, for example, the first insulating material region may be positioned near signal lines or other circuit features to reduce capacitance while using the second insulating material region near a location that is susceptible to localized mechanical stress, such as a fuse location, an external connection bonding location or a scribe line location.
摘要翻译：集成电路器件包括多个堆叠电路层，所述多个电路层中的至少一个包括复合层间绝缘层，所述复合层间绝缘层包括具有不同机械强度和介电特性的横向相邻的第一和第二绝缘材料区域，以及设置的多个电路部件在复合层间绝缘层中。第一绝缘材料区域可以具有比第二绝缘材料区域更低的介电常数和更低的机械强度，使得例如第一绝缘材料区域可以位于信号线附近或其他电路特征处以在使用第二绝缘材料区域时降低电容绝缘材料区域靠近容易受到局部机械应力的位置，诸如熔断器位置，外部连接接合位置或划线位置。

2. 发明授权

US08367535B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08367535B2
公开(公告)日：2013-02-05
申请号：US13053668
申请日：2011-03-22
申请人： Yong-Soon Choi , Ha-Young Yi , Gil-Heyun Choi , Eunkee Hong , Sang-Hoon Ahn
发明人： Yong-Soon Choi , Ha-Young Yi , Gil-Heyun Choi , Eunkee Hong , Sang-Hoon Ahn
IPC分类号： H01L21/28
CPC分类号： H01L21/28052 , H01L21/28273 , H01L21/76834 , H01L27/11521 , H01L27/11524 , H01L29/7881
摘要： Example embodiments herein relate to a method of fabricating a semiconductor device. The method may include forming a liner insulating layer on a surface of a gate pattern to have a first thickness. Subsequently, a gap fill layer may be formed on the liner insulating layer by flowable chemical vapor deposition (FCVD) or spin-on-glass (SOG). The liner insulating layer and the gap fill layer may be recessed such that the liner insulating layer has a second thickness, which is smaller than the first thickness, in the region in which a metal silicide will be formed. Metal silicide may be formed on the plurality of gate patterns to have a relatively uniform thickness using the difference in thickness of the liner insulating layer.
摘要翻译：本文的示例性实施例涉及制造半导体器件的方法。该方法可以包括在栅极图案的表面上形成具有第一厚度的衬里绝缘层。随后，可以通过可流动化学气相沉积（FCVD）或旋涂玻璃（SOG）在衬垫绝缘层上形成间隙填充层。衬垫绝缘层和间隙填充层可以凹入，使得衬垫绝缘层在其中将形成金属硅化物的区域中具有小于第一厚度的第二厚度。可以使用衬垫绝缘层的厚度差，在多个栅极图案上形成金属硅化物以具有相对均匀的厚度。

3. 发明申请

US20110281427A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20110281427A1
公开(公告)日：2011-11-17
申请号：US13053668
申请日：2011-03-22
申请人： Yong-Soon Choi , Ha-Young Yi , Gil-Heyun Choi , Eunkee Hong , Sang-Hoon Ahn
发明人： Yong-Soon Choi , Ha-Young Yi , Gil-Heyun Choi , Eunkee Hong , Sang-Hoon Ahn
IPC分类号： H01L21/28
CPC分类号： H01L21/28052 , H01L21/28273 , H01L21/76834 , H01L27/11521 , H01L27/11524 , H01L29/7881
摘要： Example embodiments herein relate to a method of fabricating a semiconductor device. The method may include forming a liner insulating layer on a surface of a gate pattern to have a first thickness. Subsequently, a gap fill layer may be formed on the liner insulating layer by flowable chemical vapor deposition (FCVD) or spin-on-glass (SOG). The liner insulating layer and the gap fill layer may be recessed such that the liner insulating layer has a second thickness, which is smaller than the first thickness, in the region in which a metal silicide will be formed. Metal silicide may be formed on the plurality of gate patterns to have a relatively uniform thickness using the difference in thickness of the liner insulating layer.
摘要翻译：本文的示例性实施例涉及制造半导体器件的方法。该方法可以包括在栅极图案的表面上形成具有第一厚度的衬里绝缘层。随后，可以通过可流动化学气相沉积（FCVD）或旋涂玻璃（SOG）在衬垫绝缘层上形成间隙填充层。衬垫绝缘层和间隙填充层可以凹入，使得衬垫绝缘层在其中将形成金属硅化物的区域中具有小于第一厚度的第二厚度。可以使用衬垫绝缘层的厚度差，在多个栅极图案上形成金属硅化物以具有相对均匀的厚度。

4. 发明申请

US20100203700A1 METHOD OF FORMING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：形成半导体器件的方法
公开(公告)号：US20100203700A1
公开(公告)日：2010-08-12
申请号：US12686638
申请日：2010-01-13
申请人： Kyungmun Byun , Deok-Young Jung , Ju-Seon Goo , Eunkee Hong
发明人： Kyungmun Byun , Deok-Young Jung , Ju-Seon Goo , Eunkee Hong
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/76832 , H01L21/76834 , H01L21/76837
摘要： A method of forming a semiconductor device includes preparing a substrate having a recessed area. A silicon oxide layer is formed at the recessed area. A catalytic nitridation treatment is performed for an upper portion of the silicon oxide layer to form a nitridation reactant on the upper portion of the silicon oxide layer. A dielectric layer is formed on the silicon oxide layer where the nitridation reactant is formed. The dielectric layer is annealed. According to the foregoing method, recession of the dielectric layer is prevented to fabricate a high-quality semiconductor device.
摘要翻译：形成半导体器件的方法包括制备具有凹陷区域的衬底。在凹陷区域形成氧化硅层。对氧化硅层的上部进行催化氮化处理，以在氧化硅层的上部形成氮化反应物。在形成氮化反应物的氧化硅层上形成介电层。电介质层退火。根据上述方法，防止了电介质层的凹陷以制造高质量的半导体器件。

5. 发明申请

US20060089008A1 Methods of manufacturing silicon oxide isolation layers and semiconductor devices that include such isolation layers 审中-公开
标题翻译：制造包含这种隔离层的氧化硅隔离层和半导体器件的方法
公开(公告)号：US20060089008A1
公开(公告)日：2006-04-27
申请号：US11259408
申请日：2005-10-26
申请人： Eunkee Hong , Ju-Seon Goo , Kyu-Tae Na , Sang-Ho Rha
发明人： Eunkee Hong , Ju-Seon Goo , Kyu-Tae Na , Sang-Ho Rha
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/76232 , H01L21/02164 , H01L21/02222 , H01L21/02282 , H01L21/02337 , H01L21/3125 , H01L21/316
摘要： Methods of manufacturing silicon oxide layers for semiconductor devices are provided in which a substrate having a recess is coated with a spin-on-glass film so that the recess is filled with the spin-on-glass film. A main thermal treatment is performed on the spin-on-glass film at about 600 to about 1,000° C. at about 1 ATM to about 50 ATM so that the spin-on-glass film is converted into a relatively dense silicon oxide layer.
摘要翻译：提供了制造用于半导体器件的氧化硅层的方法，其中具有凹陷的衬底涂覆有旋涂玻璃膜，使得凹部填充有旋涂玻璃膜。在旋转玻璃膜上进行主要的热处理，在约1 00至约1000℃，约1个ATM至约50个ATM处进行，以使旋涂玻璃膜转化成相对致密的氧化硅层。

6. 发明授权

US08835315B2 Methods of fabricating semiconductor memory devices including support patterns 有权
标题翻译：制造包括支持图案的半导体存储器件的方法
公开(公告)号：US08835315B2
公开(公告)日：2014-09-16
申请号：US13371127
申请日：2012-02-10
申请人： Kyungmun Byun , Hyongsoo Kim , Eunkee Hong , Mansug Kang
发明人： Kyungmun Byun , Hyongsoo Kim , Eunkee Hong , Mansug Kang
IPC分类号： H01L27/108 , H01L49/02
CPC分类号： H01L27/10808 , H01L27/10852 , H01L28/90
摘要： A capacitor dielectric can be between the storage node and the electrode layer. A supporting pattern can be connected to the storage node, where the supporting pattern can include at least one first pattern and at least one second pattern layered on one another, where the first pattern can include a material having an etch selectivity with respect to the second pattern.
摘要翻译：电容器电介质可以在存储节点和电极层之间。支撑图案可以连接到存储节点，其中支撑图案可以包括至少一个第一图案和彼此分层的至少一个第二图案，其中第一图案可以包括具有相对于第二图案的蚀刻选择性的材料模式。

7. 发明授权

US08298910B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08298910B2
公开(公告)日：2012-10-30
申请号：US12732907
申请日：2010-03-26
申请人： Sang-Don Nam , Sang-Hoon Ahn , Eunkee Hong
发明人： Sang-Don Nam , Sang-Hoon Ahn , Eunkee Hong
IPC分类号： H01L21/764
CPC分类号： H01L21/7682 , H01L21/0337 , H01L21/0338 , H01L21/3105 , H01L21/31144 , H01L23/5222 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Provided is a method for fabricating a semiconductor device, including forming an interconnect structure including first and second interconnects and an insulating material between the first and second interconnects, forming a first mask layer and a second mask layer having a plurality of micropores sequentially on the interconnect structure, coalescing the plurality of micropores in the second mask layer with each other and forming a plurality of first microholes in the second mask layer, forming a plurality of second microholes in the first mask layer using the plurality of first microholes, and removing the insulating material using the first mask layer with the plurality of second microholes as an etch mask so as to form an air-gap between the first and second interconnects.
摘要翻译：提供一种制造半导体器件的方法，包括在第一和第二互连之间形成包括第一和第二互连的互连结构和绝缘材料，在互连上依次形成具有多个微孔的第一掩模层和第二掩模层结构，将第二掩模层中的多个微孔彼此聚结并在第二掩模层中形成多个第一微孔，在第一掩模层中使用多个第一微孔形成多个第二微孔，并且去除绝缘使用具有多个第二微孔的第一掩模层作为蚀刻掩模的材料，以便在第一和第二互连之间形成气隙。

8. 发明申请

US20120034757A1 METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING VARIOUS ISOLATION REGIONS 有权
标题翻译：制备各种分离区域的半导体器件的方法
公开(公告)号：US20120034757A1
公开(公告)日：2012-02-09
申请号：US13162050
申请日：2011-06-16
申请人： Yong-Soon Choi , Jun-Won Lee , Gil-Heyun Choi , Eunkee Hong , Hong-Gun Kim , Ha-Young Yi
发明人： Yong-Soon Choi , Jun-Won Lee , Gil-Heyun Choi , Eunkee Hong , Hong-Gun Kim , Ha-Young Yi
IPC分类号： H01L21/762
CPC分类号： H01L21/76229 , H01L21/02222 , H01L21/02271 , H01L21/76885 , H01L27/105 , H01L27/10897 , H01L27/11531 , H01L27/11548
摘要： A method of fabricating a semiconductor device includes forming a first trench and a second trench in a semiconductor substrate, forming a first insulator to completely fill the first trench, the first insulator covering a bottom surface and lower sidewalls of the second trench and exposing upper sidewalls of the second trench, and forming a second insulator on the first insulator in the second trench.
摘要翻译：制造半导体器件的方法包括在半导体衬底中形成第一沟槽和第二沟槽，形成第一绝缘体以完全填充第一沟槽，第一绝缘体覆盖第二沟槽的底表面和下侧壁，并暴露上侧壁并且在所述第二沟槽中的所述第一绝缘体上形成第二绝缘体。

9. 发明申请

US20110306195A1 METHOD OF MANUFACTURING VERTICAL SEMICONDUCTOR DEVICES 审中-公开
标题翻译：制造垂直半导体器件的方法
公开(公告)号：US20110306195A1
公开(公告)日：2011-12-15
申请号：US13099485
申请日：2011-05-03
申请人： Jin-Gyun Kim , Bo-Young Lee , Ki-Hyun Hwang , Eunkee Hong , Jong-Wan Choi
发明人： Jin-Gyun Kim , Bo-Young Lee , Ki-Hyun Hwang , Eunkee Hong , Jong-Wan Choi
IPC分类号： H01L21/28
CPC分类号： H01L27/11578 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： In a vertical semiconductor device and a method of manufacturing a vertical semiconductor device, sacrificial layers and insulating interlayers are repeatedly and alternately stacked on a substrate. The sacrificial layers include boron (B) and nitrogen (N) and have an etching selectivity with respect to the insulating interlayers. Semiconductor patterns are formed on the substrate through the sacrificial layers and the insulating interlayers. The sacrificial layers and the insulating interlayers are at least partially removed between the semiconductor patterns to form sacrificial layer patterns and insulating interlayer patterns on sidewalls of the semiconductor patterns. The sacrificial layer patterns are removed to form grooves between the insulating interlayer patterns. The grooves expose portions of the sidewalls of the semiconductor patterns. A gate structure is formed in each of the grooves.
摘要翻译：在垂直半导体器件和制造垂直半导体器件的方法中，牺牲层和绝缘夹层重叠交替堆叠在衬底上。牺牲层包括硼（B）和氮（N），并且相对于绝缘夹层具有蚀刻选择性。通过牺牲层和绝缘夹层在衬底上形成半导体图案。在半导体图案之间至少部分去除牺牲层和绝缘夹层，以在半导体图案的侧壁上形成牺牲层图案和绝缘层间图案。去除牺牲层图案以在绝缘层间图案之间形成凹槽。凹槽暴露半导体图案的侧壁的部分。在每个槽中形成栅极结构。

10. 发明授权

US08043914B2 Methods of fabricating flash memory devices comprising forming a silicide on exposed upper and side surfaces of a control gate 有权
标题翻译：制造闪存器件的方法包括在暴露的控制栅极的上表面和侧表面上形成硅化物
公开(公告)号：US08043914B2
公开(公告)日：2011-10-25
申请号：US12629920
申请日：2009-12-03
申请人： Jong-wan Choi , Yong-soon Choi , Bo-young Lee , Eunkee Hong , Eun-kyung Baek , Ju-seon Goo
发明人： Jong-wan Choi , Yong-soon Choi , Bo-young Lee , Eunkee Hong , Eun-kyung Baek , Ju-seon Goo
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/11524
摘要： Provided are methods of fabricating flash memory devices that may prevent a short circuit from occurring between cell gate lines. Methods of fabricating such flash memory devices may include forming gate lines including a series of multiple cell gate lines and multiple selection gate lines. Each gate line may include a stacked structure of a tunnel insulating layer, a floating gate, a gate insulating layer, and/or a polysilicon layer operable to be a control gate, all formed on a semiconductor substrate. Methods may include forming a first insulating layer that selectively fills gaps between the cell gate lines from the bottom up and between adjacent ones of the cell gate lines and the selection gate lines, and does not fill a space located on outer sides of the selection gate lines that are opposite the plurality of cell gate lines. A spacer may be formed on the outer sides of the selection gate lines that are opposite to the cell gate lines, after forming the first insulating layer. A second insulating layer may be formed in a space where the spacer is formed.
摘要翻译：提供了制造闪存器件的方法，其可以防止在单元栅极线之间发生短路。制造这种闪存器件的方法可以包括形成包括一系列多单元栅极线和多个选择栅极线的栅极线。每个栅极线可以包括全部形成在半导体衬底上的隧道绝缘层，浮动栅极，栅极绝缘层和/或可操作为控制栅极的多晶硅层的堆叠结构。方法可以包括形成第一绝缘层，其选择性地从底部向上和相邻的单元栅极线和选择栅极线之间填充单元栅极线之间的间隙，并且不填充位于选择栅极的外侧的空间与多个单元栅极线相对的线。在形成第一绝缘层之后，可以在选择栅极线的与单元栅极线相对的外侧上形成间隔物。可以在形成间隔物的空间中形成第二绝缘层。

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