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1. 发明授权

US09058432B2 Data transferring circuit and data transferring/receiving system 有权
标题翻译：数据传输电路和数据传输/接收系统
公开(公告)号：US09058432B2
公开(公告)日：2015-06-16
申请号：US13334208
申请日：2011-12-22
申请人： Geun-Il Lee
发明人： Geun-Il Lee
IPC分类号： G06F13/12 , G06F13/38 , H03M9/00
CPC分类号： G06F13/38 , G06F13/423
摘要： A data transferring circuit includes a data transferor configured to transfer data through a plurality of parallel data transfer lines, wherein the data transferor is further configured to partially invert the transferred data in response to an inversion signal, and a pattern sensor configured to enable the inversion signal when data transferred through the parallel data transfer lines is to cause three sequential lines to transfer data of a logic value through a middle one of the sequential lines and data of an inverse of the logic value through the remaining ones of the sequential lines or cause all of the transfer lines to transfer data of a same logic value.
摘要翻译：数据传送电路包括：数据传送器，被配置为通过多个并行数据传送线路传送数据，其中所述数据传送器还被配置为响应于反转信号部分地反转所传送的数据;以及图案传感器，被配置为使能反转当通过并行数据传输线路传送的数据时，信号将使三条连续的线路通过顺序线路的中间线路传输逻辑值的数据，并通过其余的连续线路传输逻辑值的倒数的数据或原因所有的传输线传输相同逻辑值的数据。

2. 发明授权

US08575956B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08575956B2
公开(公告)日：2013-11-05
申请号：US13285174
申请日：2011-10-31
申请人： Geun-Il Lee
发明人： Geun-Il Lee
IPC分类号： H03K19/003
CPC分类号： H03K5/003
摘要： A semiconductor device includes an impedance control signal generation unit configured to generate an impedance control signal for controlling an impedance value, a first processing unit configured to process the impedance control signal in response to a first setup value and generate a first process signal, a first clock termination unit configured to be coupled with a first clock path and determine an impedance value responding to the impedance control signal, and a second clock termination unit configured to be coupled with a second clock path and determine an impedance value responding to the first process signal.
摘要翻译：半导体器件包括阻抗控制信号生成单元，被配置为产生用于控制阻抗值的阻抗控制信号;第一处理单元，被配置为响应于第一设定值处理阻抗控制信号并生成第一处理信号，第一处理信号时钟终端单元，被配置为与第一时钟路径耦合并且确定响应于所述阻抗控制信号的阻抗值，以及第二时钟终止单元，被配置为与第二时钟路径耦合并且确定响应于所述第一处理信号的阻抗值。

3. 发明授权

US07920008B2 Data output clock generating circuit and method of generating data output clock of semiconductor memory apparatus 有权
标题翻译：数据输出时钟生成电路及半导体存储装置的数据输出时钟的生成方法
公开(公告)号：US07920008B2
公开(公告)日：2011-04-05
申请号：US12076621
申请日：2008-03-20
申请人： Geun-Il Lee
发明人： Geun-Il Lee
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： A data output clock generating circuit for a semiconductor memory apparatus includes a rising data output clock generating unit configured to combine a rising clock with a rising clock extraction signal generated in response to a rising output enable signal and a falling clock, to generate a rising data output clock; and a falling data output clock generating unit configured to combine the falling clock with a falling clock extraction signal generated in response to a falling output enable signal and the rising clock, to generate a falling data output clock; wherein the rising data output clock generating unit and the falling data output clock generating unit are independently driven in parallel.
摘要翻译：一种用于半导体存储装置的数据输出时钟产生电路包括上升数据输出时钟产生单元，配置为将上升时钟与响应于上升输出使能信号和下降时钟产生的上升时钟提取信号进行组合，以产生上升数据输出时钟以及下降数据输出时钟生成单元，被配置为将下降时钟与响应于下降输出使能信号和上升时钟产生的下降时钟提取信号进行组合，以产生下降数据输出时钟; 其中上升数据输出时钟产生单元和下降数据输出时钟产生单元被并行驱动。

4. 发明申请

US20100308861A1 TERMINATION CIRCUIT AND IMPEDANCE MATCHING DEVICE INCLUDING THE SAME 有权
标题翻译：终止电路和阻抗匹配装置，包括它们
公开(公告)号：US20100308861A1
公开(公告)日：2010-12-09
申请号：US12494394
申请日：2009-06-30
申请人： Geun-Il Lee
发明人： Geun-Il Lee
IPC分类号： H03K17/16 , H03K19/0175
CPC分类号： H04L25/0278
摘要： An impedance matching device includes a calibration circuit configured to generate impedance calibration codes for modification of impedance; a code modification unit configured to modify the impedance calibration codes according to impedance setting information and output modified impedance calibration codes; and a termination impedance unit configured to terminate an interface node with impedance determined according to the modified impedance calibration codes.
摘要翻译：阻抗匹配装置包括：校准电路，被配置为产生用于修改阻抗的阻抗校准码; 代码修改单元，被配置为根据阻抗设置信息修改阻抗校准码并输出修改的阻抗校准码; 以及终端阻抗单元，被配置为终止具有根据修改的阻抗校准码确定的阻抗的接口节点。

5. 发明授权

US07679986B2 Data latch controller of synchronous memory device 有权
标题翻译：同步存储器件的数据锁存控制器
公开(公告)号：US07679986B2
公开(公告)日：2010-03-16
申请号：US12047429
申请日：2008-03-13
申请人： Geun Il Lee
发明人： Geun Il Lee
IPC分类号： G11C8/00
CPC分类号： G11C7/1078 , G11C7/1066 , G11C7/1072 , G11C7/1087 , G11C7/1093 , G11C7/1096 , G11C7/22 , G11C11/4076 , G11C11/4096
摘要： Disclosed is a data input circuit of a synchronous memory device for detecting and amplifying data, and transferring the amplified data for storage, which including: a write strobe signal converter for receiving a write strobe signal, dividing the received write strobe signal, and outputting control signals of predetermined bits, the control signals being synchronized with rising and falling edges of the divided signal; and a latch unit for latching data corresponding to the bits by means of the control signals, and outputting the data for the detection and amplification of the data. The data input circuit may include a first delay unit for delaying the data in order to match setup-hold time, a second delay unit for performing delay for adjusting the data outputted from the latch unit, and a third delay unit for performing delay for adjusting the write strobe signal outputted from the latch unit.
摘要翻译：公开了一种用于检测和放大数据并传送放大的数据用于存储的同步存储装置的数据输入电路，包括：写入选通信号转换器，用于接收写选通信号，分频接收的写选通信号，并输出控制控制信号与分频信号的上升沿和下降沿同步; 以及锁存单元，用于通过控制信号锁存与位对应的数据，并输出用于数据的检测和放大的数据。数据输入电路可以包括用于延迟数据以匹配建立保持时间的第一延迟单元，用于执行用于调整从锁存单元输出的数据的延迟的第二延迟单元，以及用于执行延迟调整的第三延迟单元从锁存单元输出的写选通信号。

6. 发明申请

US20050226060A1 Semiconductor memory device including global IO line with low-amplitude driving voltage signal applied thereto 有权
标题翻译：半导体存储器件包括施加有低幅度驱动电压信号的全局IO线
公开(公告)号：US20050226060A1
公开(公告)日：2005-10-13
申请号：US10980663
申请日：2004-11-03
申请人： Geun-il Lee , Yong-suk Joo
发明人： Geun-il Lee , Yong-suk Joo
IPC分类号： G11C7/00 , G11C7/10 , G11C11/4093
CPC分类号： G11C11/4093 , G11C7/1006 , G11C7/1048
摘要： Disclosed is a semiconductor memory device including a global IO line with a low-amplitude driving voltage signal applied thereto. In the device, a first driver converts a data signal of a first voltage level from a memory cell to a second voltage level in response to a read control signal, and outputs it to a global IO line. A first level shifter converts the data signal of the second voltage level from the line back to the first voltage level, and outputs it to a data output terminal. A second driver converts an external data signal of a first voltage level from a data input terminal to a second voltage level, and outputs it to a global IO line. A second level shifter converts the external data signal of the second voltage level from the line back to the first voltage level and outputs it to a write driver.
摘要翻译：公开了一种包括施加有低振幅驱动电压信号的全局IO线的半导体存储器件。在该装置中，第一驱动器响应于读取控制信号将来自存储器单元的第一电压电平的数据信号转换为第二电压电平，并将其输出到全局IO线。第一电平移位器将第二电压电平的数据信号从线路转换回第一电压电平，并将其输出到数据输出端子。第二驱动器将来自数据输入端的第一电压电平的外部数据信号转换为第二电压电平，并将其输出到全局IO线。第二电平移位器将第二电压电平的外部数据信号从线路转换回第一电压电平，并将其输出到写入驱动器。

7. 发明授权

US06845031B2 Nonvolatile ferroelectric memory device and method for driving the same 有权
标题翻译：非易失性铁电存储器件及其驱动方法
公开(公告)号：US06845031B2
公开(公告)日：2005-01-18
申请号：US10326916
申请日：2002-12-23
申请人： Hee Bok Kang , Hun Woo Kye , Geun Il Lee , Je Hoon Park , Jung Hwan Kim
发明人： Hee Bok Kang , Hun Woo Kye , Geun Il Lee , Je Hoon Park , Jung Hwan Kim
IPC分类号： G11C11/22 , G11C7/00
CPC分类号： G11C11/22
摘要： A nonvolatile ferroelectric memory device and a method for driving the same are disclosed, the device and method devised to stabilize the operation processes and reduce the operation time. The nonvolatile ferroelectric memory device includes a cell array block having a plurality of unit cells being controlled by plate lines and wordlines, a plate line driver being positioned on one side of the cell array block to apply a driving signal to the plate lines, a wordline driver being positioned on the other side of the cell array block to apply a driving signal to the wordlines, a plurality of sub bitlines and main bitlines being arranged on the cell array block in the same direction, and switching control blocks controlling signals applied to the sub bitlines and main bitlines.
摘要翻译：公开了一种非易失性铁电存储器件及其驱动方法，该装置和方法旨在稳定操作过程并减少操作时间。非易失性铁电存储器件包括具有由板线和字线控制的多个单位电池的单元阵列块，位于单元阵列块一侧的板线驱动器，以向板线施加驱动信号，字线驱动器位于单元阵列块的另一侧，以将驱动信号施加到字线，多个子位线和主位线沿相同方向布置在单元阵列块上，并且控制块控制施加到单元阵列块的信号次位线和主要位线。

8. 发明授权

US06700812B2 Nonvolatile ferroelectric memory device and method for driving the same 有权
标题翻译：非易失性铁电存储器件及其驱动方法
公开(公告)号：US06700812B2
公开(公告)日：2004-03-02
申请号：US10251848
申请日：2002-09-23
申请人： Hee Bok Kang , Hun Woo Kye , Geun Il Lee , Je Hoon Park , Jung Hwan Kim
发明人： Hee Bok Kang , Hun Woo Kye , Geun Il Lee , Je Hoon Park , Jung Hwan Kim
IPC分类号： G11C1122
CPC分类号： G11C11/22 , G11C11/5657
摘要： A nonvolatile ferroelectric memory device includes a first cell array block and a second cell array block, each divided into an upper part and a lower part; sensing amplifiers arranged one by one on multiple bit lines at a middle portion between the first cell array block and the second cell array block; a data I/O encoder connected to end portions of the multiple bit lines for outputting multi-bit signals by encoding outputs of the sensing amplifiers; and a first reference cell array block and a second reference cell array block arranged between the first cell array block and the data I/O encoder and between the second cell array block and the data I/O encoder.
摘要翻译：非易失性铁电存储器件包括第一单元阵列块和第二单元阵列块，每个分隔成上部和下部; 在第一单元阵列块和第二单元阵列块之间的中间部分的多个位线上逐个布置的感测放大器; 连接到多位线的端部的数据I / O编码器，用于通过对感测放大器的输出进行编码来输出多位信号; 以及布置在第一单元阵列块和数据I / O编码器之间以及第二单元阵列块和数据I / O编码器之间的第一参考单元阵列块和第二参考单元阵列块。

9. 发明申请

US20130162286A1 IMPEDANCE CODE GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 审中-公开
标题翻译：阻抗代码生成电路和包含其的半导体存储器件
公开(公告)号：US20130162286A1
公开(公告)日：2013-06-27
申请号：US13595427
申请日：2012-08-27
申请人： Geun-Il LEE
发明人： Geun-Il LEE
IPC分类号： H03K19/003
CPC分类号： H03K19/00315 , H03K19/018571 , H03K19/018585
摘要： An impedance code generation circuit includes an impedance code generation unit configured to generate an impedance code, a set value generation unit configured to generate a set value by counting an external signal, and an impedance code modification unit configured to generate a modified impedance code by performing a logic operation on the set value and the impedance code.
摘要翻译：阻抗代码产生电路包括：阻抗代码生成单元，被配置为产生阻抗代码;设定值生成单元，被配置为通过对外部信号进行计数来产生设定值;以及阻抗代码修改单元，被配置为通过执行对设定值和阻抗代码进行逻辑运算。

10. 发明授权

US07944233B1 Data output circuit 有权
标题翻译：数据输出电路
公开(公告)号：US07944233B1
公开(公告)日：2011-05-17
申请号：US12647114
申请日：2009-12-24
申请人： Geun-Il Lee
发明人： Geun-Il Lee
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： G11C7/1051 , G11C7/1057 , H03K19/01707 , H04L25/028
摘要： A data output circuit includes a plurality of drivers configured to be turned on/off according to impedance codes to output data to an output node. The impedance codes are divided into a first group having a value to turn on the drivers, and a second group having a value to turn off the drivers, and at least some of the drivers controlled by the second group are turned on during a pre-emphasis period.
摘要翻译：数据输出电路包括多个根据阻抗代码被配置为导通/截止的驱动器，以将数据输出到输出节点。阻抗代码被分成具有打开驱动器的值的第一组，以及具有关闭驱动器的值的第二组，并且由第二组控制的至少一些驱动器在预处理期间被导通，强调期

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