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1. 发明授权

US09118351B2 System and method for signature-based redundancy comparison 有权
标题翻译：用于基于签名的冗余比较的系统和方法
公开(公告)号：US09118351B2
公开(公告)日：2015-08-25
申请号：US13430126
申请日：2012-03-26
申请人： Antonio Vilela , Rainer Faller , Michael Goessel , Simon Brewerton , Glenn Ashley Farrall , Neil Stuart Hastie , Boyko Traykov , David Addison , Klaus Oberlaender , Thomas Rabenalt
发明人： Antonio Vilela , Rainer Faller , Michael Goessel , Simon Brewerton , Glenn Ashley Farrall , Neil Stuart Hastie , Boyko Traykov , David Addison , Klaus Oberlaender , Thomas Rabenalt
IPC分类号： G06F11/00 , H03M13/37 , G05B19/042 , G05B9/03 , G06F11/16 , G06F11/10 , G06F11/14 , H03M13/03 , H03M13/15 , H03M13/19 , H03M13/25 , H03M13/29 , H03M13/00
CPC分类号： H03M13/3746 , G05B9/03 , G05B19/0428 , G06F11/00 , G06F11/1048 , G06F11/1479 , G06F11/1641 , H03M13/033 , H03M13/155 , H03M13/19 , H03M13/258 , H03M13/2948 , H03M13/2957 , H03M13/2966 , H03M13/299 , H03M13/37 , H03M13/3738 , H03M13/3784 , H03M13/6575
摘要： A system and method for signature-based redundancy comparison provides for receiving, by a master part, an input signal and generating, by the master part, a binary output signal, generating a delayed input signal based on the input signal, generating a first output signature based on the binary output signal, and generating a delayed first output signature based on the first output signature. The system and method further comprise generating a delayed binary output signal based on the delayed input signal, generating, by a checker part, a delayed second output signature based on the delayed binary output signal, comparing the delayed first output signature with the delayed second output signature, and generating an error signal, where the state of the error signal is based upon the comparison.
摘要翻译：一种用于基于签名的冗余比较的系统和方法，用于由主机部分接收输入信号，并由主机部分产生二进制输出信号，基于输入信号产生延迟的输入信号，产生第一输出基于所述二进制输出信号的签名，以及基于所述第一输出签名生成延迟的第一输出签名。该系统和方法还包括基于延迟的输入信号产生延迟的二进制输出信号，由检验器部分基于延迟的二进制输出信号产生延迟的第二输出签名，将延迟的第一输出签名与延迟的第二输出进行比较签名并产生误差信号，其中误差信号的状态基于比较。

2. 发明授权

US06457118B1 Method and system for selecting and using source operands in computer system instructions 有权
标题翻译：在计算机系统指令中选择和使用源操作数的方法和系统
公开(公告)号：US06457118B1
公开(公告)日：2002-09-24
申请号：US09410549
申请日：1999-10-01
申请人： Chih-Jui Peng , Glenn Ashley Farrall , Sivaram Krishnan
发明人： Chih-Jui Peng , Glenn Ashley Farrall , Sivaram Krishnan
IPC分类号： G06F938
CPC分类号： G06F9/30167 , G06F9/30101 , G06F9/3016 , G06F9/383 , G06F9/3836 , G06F9/3838
摘要： According to the present invention, techniques for setting selected operand fields in pipelined architectures are provided. Methods and systems for efficiently selecting operand fields according to the present invention can be operative on a variety of computer architectures, including RISC architectures.
摘要翻译：根据本发明，提供了用于在流水线架构中设置所选操作数字段的技术。根据本发明的用于有效选择操作数字段的方法和系统可以在各种计算机体系结构（包括RISC体系结构）上运行。

3. 发明授权

US08560899B2 Safe memory storage by internal operation verification 有权
标题翻译：通过内部操作验证安全内存存储
公开(公告)号：US08560899B2
公开(公告)日：2013-10-15
申请号：US12847450
申请日：2010-07-30
申请人： Simon Brewerton , Neil Hastie , Paul Hubbert , Klaus Oberlaender , Robert Wiesner , Antonio Vilela , Alfred Eder , Glenn Ashley Farrall
发明人： Simon Brewerton , Neil Hastie , Paul Hubbert , Klaus Oberlaender , Robert Wiesner , Antonio Vilela , Alfred Eder , Glenn Ashley Farrall
IPC分类号： G06F11/00
CPC分类号： G11C29/44 , G11C29/024 , G11C29/025 , G11C2029/0411
摘要： The disclosed invention provides a structure and method for detecting address line (e.g., wordline, bitline) memory failures. In one embodiment, the method and structure comprise generating an address signature, by re-encoding an internally generated address signal from activated elements (e.g., wordlines) inside a memory array. The regenerated address signature may be compared with a requested memory address location. If the regenerated address signature and memory location are equal than there is no error in the memory array, but if the regenerated address signature and memory location are equal than an error is present in the memory array. Accordingly, re-encoding an address signature provides a closed loop check that a wordline and/or bitline, that was actually activated in a memory array, was the correct requested wordline and/or bitline, that no other wordlines or bitlines were also triggered, and that the wordline and/or bitline is continuous.
摘要翻译：所公开的发明提供了用于检测地址线（例如，字线，位线）存储器故障的结构和方法。在一个实施例中，该方法和结构包括通过从存储器阵列内部的激活元件（例如，字线）重新编码内部产生的地址信号来生成地址签名。再生地址签名可以与请求的存储器地址位置进行比较。如果再生地址签名和存储器位置等于存储器阵列中没有错误，但是如果再生地址签名和存储器位置等于存储器阵列中存在错误。因此，对地址签名的重新编码提供闭环检查，即在存储器阵列中实际激活的字线和/或位线是正确请求的字线和/或位线，没有其他字线或位线也被触发，字线和/或位线是连续的。

4. 发明申请

US20130212441A1 System and Method for Signature-Based Redundancy Comparison 有权
标题翻译：基于签名的冗余比较系统与方法
公开(公告)号：US20130212441A1
公开(公告)日：2013-08-15
申请号：US13430126
申请日：2012-03-26
申请人： Antonio Vilela , Rainer Faller , Michael Goessel , Simon Brewerton , Glenn Ashley Farrall , Neil Stuart Hastie , Boyko Traykov , David Addison , Klaus Oberlaender , Thomas Rabenalt
发明人： Antonio Vilela , Rainer Faller , Michael Goessel , Simon Brewerton , Glenn Ashley Farrall , Neil Stuart Hastie , Boyko Traykov , David Addison , Klaus Oberlaender , Thomas Rabenalt
IPC分类号： G06F11/07
CPC分类号： H03M13/3746 , G05B9/03 , G05B19/0428 , G06F11/00 , G06F11/1048 , G06F11/1479 , G06F11/1641 , H03M13/033 , H03M13/155 , H03M13/19 , H03M13/258 , H03M13/2948 , H03M13/2957 , H03M13/2966 , H03M13/299 , H03M13/37 , H03M13/3738 , H03M13/3784 , H03M13/6575
摘要： A system and method for signature-based redundancy comparison provides for receiving, by a master part, an input signal and generating, by the master part, a binary output signal, generating a delayed input signal based on the input signal, generating a first output signature based on the binary output signal, and generating a delayed first output signature based on the first output signature. The system and method further comprise generating a delayed binary output signal based on the delayed input signal, generating, by a checker part, a delayed second output signature based on the delayed binary output signal, comparing the delayed first output signature with the delayed second output signature, and generating an error signal, where the state of the error signal is based upon the comparison.
摘要翻译：一种用于基于签名的冗余比较的系统和方法，用于由主机部分接收输入信号，并由主机部分产生二进制输出信号，基于输入信号产生延迟的输入信号，产生第一输出基于所述二进制输出信号的签名，以及基于所述第一输出签名生成延迟的第一输出签名。该系统和方法还包括基于延迟的输入信号产生延迟的二进制输出信号，由检验器部分基于延迟的二进制输出信号产生延迟的第二输出签名，将延迟的第一输出签名与延迟的第二输出进行比较签名并产生误差信号，其中误差信号的状态基于比较。

5. 发明授权

US06460105B1 Method and system for transmitting interrupts from a peripheral device to another device in a computer system 有权
标题翻译：用于在计算机系统中从外围设备向另一设备发送中断的方法和系统
公开(公告)号：US06460105B1
公开(公告)日：2002-10-01
申请号：US09302685
申请日：1999-04-29
申请人： Andrew Michael Jones , Andrew Keith Betts , Glenn Ashley Farrall , Brian Foster , Andrew Craig Sturges
发明人： Andrew Michael Jones , Andrew Keith Betts , Glenn Ashley Farrall , Brian Foster , Andrew Craig Sturges
IPC分类号： G06F1324
CPC分类号： G06F13/24
摘要： The transmission of interrupts is described where the interrupt is represented at a peripheral device by the electrical level of a conductor but where it is conveyed to a receiving module by way of a message packet routed along a routing path. According to one aspect, the message packet includes the identification of the peripheral device which generated the interrupt and the receiving module acts on the message packet to implement an interrupt handling routine depending on the identification of the peripheral device. According to another aspect, the message packet includes a transaction identifier which uniquely identifies one of a series of interrupts, and the receiving module generates a response packet containing that transaction identifier thereby allowing the peripheral device to monitor whether or not its interrupts have been treated properly.
摘要翻译：描述了中断的传输，其中中断在外围设备处由导体的电平表示，但是通过沿着路由路径路由的消息分组被传送到接收模块。根据一方面，消息分组包括产生中断的外围设备的标识，并且接收模块根据外围设备的标识来执行消息分组以实现中断处理例程。根据另一方面，消息分组包括唯一地标识一系列中断之一的事务标识符，并且接收模块生成包含该事务标识符的响应分组，从而允许外围设备监视其中断是否已被正确处理。

6. 发明授权

US06378064B1 Microcomputer 有权
标题翻译：微电脑
公开(公告)号：US06378064B1
公开(公告)日：2002-04-23
申请号：US09267057
申请日：1999-03-12
申请人： David Alan Edwards , Glenn Ashley Farrall
发明人： David Alan Edwards , Glenn Ashley Farrall
IPC分类号： G06F9305
CPC分类号： G06F11/3648 , G06F11/348
摘要： A computer system comprising a microprocessor on a single integrated circuit chip having an on-chip CPU which includes: a data processing unit for executing instructions; a data link connected between a memory and the data processing unit for passing instructions to the data processing unit; a watch register for storing an instruction comparison code; and a watch comparator coupled to the data link for comparing the instructions passed on the data link with the instruction comparison code and generating a comparison output signal in dependence on the result of the comparison.
摘要翻译：一种计算机系统，包括具有片上CPU的单个集成电路芯片上的微处理器，其包括：用于执行指令的数据处理单元; 连接在存储器和数据处理单元之间的数据链路，用于将指令传递给数据处理单元; 用于存储指令比较码的监视寄存器; 以及观察比较器，其耦合到数据链路，用于将在数据链路上传递的指令与指令比较代码进行比较，并根据比较结果生成比较输出信号。

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