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1. 发明授权

US10334720B1 Printed circuit board test coupon for electrical testing during thermal exposure and method of using the same 有权
公开(公告)号：US10334720B1
公开(公告)日：2019-06-25
申请号：US16209853
申请日：2018-12-04
申请人： Greater Asia Pacific Limited
发明人： Robert Neves
IPC分类号： G01R31/28 , H05K1/02 , H05K3/42
摘要： A printed circuit board (PCB) test coupon for thermal exposure and electrical testing includes a double sided or multi-layer substrate with a plurality of vias formed within the substrate of the test coupon (blind, buried, stacked vias) or extending through the entire substrate (through hole/via) from a first surface on the first side of the plated hole/via to a second surface on the second side of the plated hole/via. Each of a first plurality of trace patterns interconnect a subset of the plurality of plated holes/vias on the first side of the plated holes/vias, and each of a second plurality of trace patterns interconnect a different subset of the plurality of plated holes/vias on the second side of the plated holes/vias. The first and second pluralities of trace patterns have different patterns and connect to connection points in a connector pattern defined in the substrate. One of the second plurality of trace patterns is configured to measure temperature and two of the second plurality of trace patterns are configured to measure calibration/drift by resistance measurements. The test coupon provides test nets that include a single plated hole/via, and optionally includes daisy chain test nets. A resistance measurement of each plated hole/via (or daisy chain) is provided by connecting 2 wires of a 4-wire kelvin bridge measurement system to the first and second sides of the plated hole/via (or daisy chain) using connection points for one of the first plurality of trace patterns and one of the second plurality of trace patterns that connect to each side of the said plated hole/via (or daisy chain).

2. 发明授权

US10379153B1 Printed circuit board test coupon for electrical testing during thermal exposure and method of using the same 有权
公开(公告)号：US10379153B1
公开(公告)日：2019-08-13
申请号：US16399470
申请日：2019-04-30
申请人： Greater Asia Pacific Limited
发明人： Robert Neves
IPC分类号： G01R31/28 , H05K1/02 , H05K1/11
摘要： A printed circuit board (PCB) test coupon for thermal exposure and electrical testing includes a double sided or multi-layer substrate with a plurality of vias formed within the substrate of the test coupon (blind, buried, stacked vias) or extending through the entire substrate (through hole/via) from a first surface on the first side of the plated hole/via to a second surface on the second side of the plated hole/via. Each of a first plurality of trace patterns interconnect a subset of the plurality of plated holes/vias on the first side of the plated holes/vias, and each of a second plurality of trace patterns interconnect a different subset of the plurality of plated holes/vias on the second side of the plated holes/vias. The first and second pluralities of trace patterns have different patterns and connect to connection points in a connector pattern defined in the substrate. One of the second plurality of trace patterns is configured to measure temperature and two of the second plurality of trace patterns are configured to measure calibration/drift by resistance measurements. The test coupon provides test nets that include a single plated hole/via, and optionally includes daisy chain test nets. A resistance measurement of each plated hole/via (or daisy chain) is provided by connecting 2 wires of a 4-wire kelvin bridge measurement system to the first and second sides of the plated hole/via (or daisy chain) using connection points for one of the first plurality of trace patterns and one of the second plurality of trace patterns that connect to each side of the said plated hole/via (or daisy chain).

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