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1. 发明授权

US08635685B2 Value generator coupled to firewall programmable qualifier data structure logics 有权
标题翻译：价值产生器耦合到防火墙可编程限定符数据结构逻辑
公开(公告)号：US08635685B2
公开(公告)日：2014-01-21
申请号：US12954093
申请日：2010-11-24
申请人： Gregory R. Conti , Jerome Azema
发明人： Gregory R. Conti , Jerome Azema
IPC分类号： G06F9/00 , G06F15/16 , G06F17/00 , G06F7/04 , G06F17/30 , H04L29/06
CPC分类号： G06F21/74
摘要： A system comprising a first logic adapted to use qualifiers received from a component to determine which of a plurality of storages matches the qualifiers, the first logic generates a first signal indicative of a storage matching the qualifiers. The system also comprises a second logic coupled to the first logic and adapted to use a target address received from the component to determine which of the plurality of storages matches the target address, the second logic generates a second signal indicative of a storage matching the target address. Another logic is adapted to determine whether the storage associated with the first signal matches the storage associated with the second signal. The qualifiers indicate security mode attributes associated with the component.
摘要翻译：一种系统，包括适于使用从组件接收的限定符来确定多个存储器中的哪一个与限定符匹配的第一逻辑，第一逻辑生成指示与限定符匹配的存储的第一信号。该系统还包括耦合到第一逻辑的第二逻辑，并且适于使用从组件接收的目标地址来确定多个存储器中的哪一个与目标地址匹配，第二逻辑生成指示与目标相匹配的存储器的第二信号地址。另一个逻辑适于确定与第一信号相关联的存储器是否与与第二信号相关联的存储器匹配。限定符表示与组件关联的安全模式属性。

2. 发明授权

US08347012B2 Interrupt morphing and configuration, circuits, systems, and processes 有权
标题翻译：中断变形和配置，电路，系统和过程
公开(公告)号：US08347012B2
公开(公告)日：2013-01-01
申请号：US12688176
申请日：2010-01-15
申请人： Steven Goss , Gregory R. Conti
发明人： Steven Goss , Gregory R. Conti
IPC分类号： G06F13/24
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , G06F9/4812 , G06F21/74 , Y02D10/126 , Y02D10/172 , Y02D10/24
摘要： An electronic configuration circuit includes a processing circuit (2610) operable for executing instructions and responsive to interrupt requests and operable in a plurality of execution environments (EE) selectively wherein a said execution environment (EE) is activated or suspended, a first configuration register (SCR) coupled to the processing circuit (2610) for identifying the interrupt request as an ordinary interrupt request IRQ when the execution environment (EE) is activated (EE_Active); and a second configuration register (SSM_FIQ_EE_y) for associating an identification of that execution environment (EE) with the same interrupt request, the processing circuit (2610) coupled (5910) to the second configuration register (SSM_FIQ_EE_y) to respond to the same interrupt request as a more urgent type of interrupt request when that execution environment (EE) is suspended (5920).
摘要翻译：电子配置电路包括可操作用于执行指令并响应于中断请求并且可选择性地在多个执行环境（EE）中操作的处理电路（2610），其中所述执行环境（EE）被激活或暂停，第一配置寄存器 SCR），其用于当所述执行环境（EE）被激活时（EE_Active）将所述中断请求识别为普通中断请求IRQ; 以及用于将所述执行环境（EE）的标识与相同的中断请求相关联的第二配置寄存器（SSM_FIQ_EE_y），所述处理电路（2610）耦合到所述第二配置寄存器（SSM_FIQ_EE_y）以响应相同的中断请求作为执行环境（EE）被暂停时的更紧急的中断请求类型（5920）。

3. 发明授权

US08307416B2 Data structures for use in firewalls 有权
标题翻译：用于防火墙的数据结构
公开(公告)号：US08307416B2
公开(公告)日：2012-11-06
申请号：US11755482
申请日：2007-05-30
申请人： Gregory R. Conti
发明人： Gregory R. Conti
IPC分类号： G06F9/00 , G06F15/16 , G06F17/00 , G06F7/04 , G06F17/30 , G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/1483 , G06F2221/2101 , G06F2221/2105 , G06F2221/2141 , H04L63/126
摘要： A system-on-chip (SOC) that includes a plurality of initiator components, and a target memory component coupled to the initiator components and having a target firewall, wherein the target firewall is configured to be programmed with a data structure which indicates, for at least one portion of the target memory component, access conditions for each initiator component.
摘要翻译：包括多个启动器组件的片上系统（SOC）以及耦合到发起者组件并具有目标防火墙的目标存储器组件，其中目标防火墙被配置为用数据结构进行编程，该数据结构指示用于目标存储器组件的至少一部分，用于每个启动器组件的访问条件。

4. 发明授权

US08185952B2 Static and dynamic firewalls 有权
标题翻译：静态和动态防火墙
公开(公告)号：US08185952B2
公开(公告)日：2012-05-22
申请号：US11678219
申请日：2007-02-23
申请人： Gregory R. Conti
发明人： Gregory R. Conti
IPC分类号： G06F21/00
CPC分类号： G06F21/79 , G06F12/1441 , G06F12/1491 , G06F21/52 , G06F21/554 , G06F21/71 , G06F21/74
摘要： A system comprising control logic adapted to activate multiple security levels for the system. The system further comprises a storage coupled to the control logic and comprising a stack, the stack associated with one, but not all, of the multiple security levels. The system also comprises security logic coupled to the control logic and adapted to restrict usage of the system if the control logic attempts to fetch an instruction op-code from the stack.
摘要翻译：一种包括适于激活系统的多个安全级别的控制逻辑的系统。该系统还包括耦合到控制逻辑并包括堆栈的存储器，该堆栈与多个安全级别中的一个但不是全部相关联。该系统还包括耦合到控制逻辑的安全逻辑，并且如果控制逻辑试图从堆栈获取指令操作码，则适用于限制系统的使用。

5. 发明授权

US07669243B2 Method and system for detection and neutralization of buffer overflow attacks 有权
标题翻译：用于检测和中和缓冲区溢出攻击的方法和系统
公开(公告)号：US07669243B2
公开(公告)日：2010-02-23
申请号：US11199427
申请日：2005-08-08
申请人： Gregory R. Conti
发明人： Gregory R. Conti
IPC分类号： G06F11/00 , H04L9/32 , H04L9/00
CPC分类号： G06F21/52 , G06F21/71
摘要： A method for detecting a stack buffer overflow attack is provided that includes receiving a memory access request from a processor core of a system, and determining that the memory access request indicates a stack buffer overflow attack. The method may further include preventing completion of the memory access request and/or executing a security violation response. A system is also provided that includes a processor core coupled to a plurality of busses and an execution stack in a random access memory coupled to the plurality of busses. The system further includes a buffer overflow protection (BOP) logic coupled to the plurality of busses to receive memory access requests from the plurality of busses. The BOP logic is operable to detect a buffer overflow attack comprising a memory access request addressing the execution stack initiated by a program executing on the processor core.
摘要翻译：提供了一种用于检测堆栈缓冲器溢出攻击的方法，包括从系统的处理器核心接收存储器访问请求，并确定存储器访问请求指示堆栈缓冲区溢出攻击。该方法还可以包括防止存储器访问请求的完成和/或执行安全违规响应。还提供了一种系统，其包括耦合到多个总线的处理器核心和耦合到多个总线的随机存取存储器中的执行堆栈。该系统还包括耦合到多个总线的缓冲器溢出保护（BOP）逻辑，以从多个总线接收存储器访问请求。 BOP逻辑可操作以检测缓冲器溢出攻击，其包括寻址由在处理器核上执行的程序发起的执行堆栈的存储器访问请求。

6. 发明申请

US20080163358A1 INITIATOR AND TARGET FIREWALLS 审中-公开
标题翻译：发起人和目标企业
公开(公告)号：US20080163358A1
公开(公告)日：2008-07-03
申请号：US11755499
申请日：2007-05-30
申请人： Gregory R. Conti
发明人： Gregory R. Conti
IPC分类号： G06F15/16
CPC分类号： G06F21/74
摘要： A system comprising a first logic adapted to use qualifiers received from a component to determine which of a plurality of storages matches the qualifiers, the first logic generates a first signal indicative of a storage matching the qualifiers. The system also comprises a second logic coupled to the first logic and adapted to use a target address received from the component to determine which of the plurality of storages matches the target address, the second logic generates a second signal indicative of a storage matching the target address. Another logic is adapted to determine whether the storage associated with the first signal matches the storage associated with the second signal. The qualifiers indicate security mode attributes associated with the component.
摘要翻译：一种系统，包括适于使用从组件接收的限定符来确定多个存储器中的哪一个与限定符匹配的第一逻辑，第一逻辑生成指示与限定符匹配的存储的第一信号。该系统还包括耦合到第一逻辑的第二逻辑，并且适于使用从组件接收的目标地址来确定多个存储器中的哪一个与目标地址匹配，第二逻辑生成指示与目标相匹配的存储器的第二信号地址。另一个逻辑适于确定与第一信号相关联的存储器是否与与第二信号相关联的存储器匹配。限定符表示与组件关联的安全模式属性。

7. 发明申请

US20080155273A1 Automatic Bus Encryption And Decryption 审中-公开
标题翻译：自动总线加密和解密
公开(公告)号：US20080155273A1
公开(公告)日：2008-06-26
申请号：US11619738
申请日：2007-01-04
申请人： Gregory R. Conti
发明人： Gregory R. Conti
IPC分类号： G06F12/14
CPC分类号： G06F12/1408 , G06F12/0897 , G06F12/1425
摘要： A system, method, and logic are disclosed for automatic hardware bus encryption/decryption. The logic receives a memory access request comprising a physical address of a memory location from a processor. The logic translates the physical address, and uses the translated physical address and a seed value in a pseudo random number generator to produce an output value. The logic then uses the output value to non-deterministically select an encryption key from a plurality of encryption keys. If the memory access request is a read operation, the logic uses the selected key to decrypt the contents of the memory location; and provides the decrypted contents to the processor. If the memory access request is a write operation, the logic uses the selected key to encrypt a value comprised in the memory access request; and writes the encrypted value in the memory location.
摘要翻译：公开了用于自动硬件总线加密/解密的系统，方法和逻辑。该逻辑从处理器接收包括存储器位置的物理地址的存储器访问请求。逻辑翻译物理地址，并使用翻译后的物理地址和伪随机数生成器中的种子值来产生输出值。逻辑然后使用输出值从多个加密密钥中非确定性地选择加密密钥。如果存储器访问请求是读取操作，则逻辑使用所选择的密钥来解密存储器位置的内容; 并将解密的内容提供给处理器。如果存储器访问请求是写入操作，则逻辑使用所选择的密钥对包含在存储器访问请求中的值进行加密; 并将加密的值写入存储器位置。

8. 发明授权

US08812804B2 Methods, apparatus, and systems for secure demand paging and other paging operations for processor devices 有权
标题翻译：用于处理器设备的安全需求寻呼和其他寻呼操作的方法，装置和系统
公开(公告)号：US08812804B2
公开(公告)日：2014-08-19
申请号：US13345484
申请日：2012-01-06
申请人： Steven C. Goss , Gregory R. Conti , Narendar Shankar , Mehdi-Laurent Akkar , Aymeric Vial
发明人： Steven C. Goss , Gregory R. Conti , Narendar Shankar , Mehdi-Laurent Akkar , Aymeric Vial
IPC分类号： G06F12/14 , G06F12/12 , G06F12/00 , G06F12/02 , H04B1/38 , H04L29/06 , H04W12/06 , G06F21/57 , G06F21/79
CPC分类号： H04L9/3236 , G06F9/45558 , G06F9/461 , G06F12/0246 , G06F12/08 , G06F12/1408 , G06F12/145 , G06F12/1483 , G06F21/575 , G06F21/79 , G06F2009/45583 , G06F2009/45587 , G06F2212/171 , G06F2212/402 , G06F2212/7201 , H04L9/0897 , H04L63/123 , H04L63/18 , H04L63/20 , H04W12/06 , H04W12/10
摘要： A secure demand paging (SDP) system includes a dynamic random access memory (DRAM), a microprocessor having a secure internal memory and coupled to said DRAM, and a non-volatile memory storing a representation of operations accessible by the microprocessor. The stored representation of operations includes a coded physical representation of operations to configure an SDP space in the DRAM, to organize the SDP space into virtual machine contexts, to organize at least one of the virtual machine contexts into block book keeping blocks and book keeping spaces in the block book keeping blocks, and to execute a secure demand paging process between said secure internal memory and said DRAM.
摘要翻译：安全需求寻呼（SDP）系统包括动态随机存取存储器（DRAM），具有安全内部存储器并耦合到所述DRAM的微处理器以及存储由微处理器访问的操作表示的非易失性存储器。存储的操作表示包括用于配置DRAM中的SDP空间的操作的编码物理表示，以将SDP空间组织成虚拟机上下文，以将虚拟机上下文中的至少一个组织成块保存块和保存空间并且在所述安全内部存储器和所述DRAM之间执行安全需求寻呼处理。

9. 发明授权

US07809934B2 Security measures for preventing attacks that use test mechanisms 有权
标题翻译：防止使用测试机制的攻击的安全措施
公开(公告)号：US07809934B2
公开(公告)日：2010-10-05
申请号：US11741181
申请日：2007-04-27
申请人： Gregory R. Conti , Pascal Cussonneau , Benoit Drevet , Vincent Chalendard
发明人： Gregory R. Conti , Pascal Cussonneau , Benoit Drevet , Vincent Chalendard
IPC分类号： G06F9/00 , G06F12/14
CPC分类号： G06F21/575 , G06F21/74 , G06F2221/2143
摘要： A system comprising processing logic adapted to determine a type of boot performed by the system and a storage coupled to the processing logic. The processing logic is configured to erase or invalidate a predetermined portion of the storage, and to activate or deactivate an interface by which the system is accessed, if the type of boot comprises a functional boot.
摘要翻译：一种系统，包括适于确定由系统执行的引导类型的处理逻辑和耦合到处理逻辑的存储。处理逻辑被配置为擦除或者使存储器的预定部分无效，并且如果引导类型包括功能引导，则激活或停用系统被访问的接口。

10. 发明授权

US08055828B2 Electronic power management system 有权
标题翻译：电子电源管理系统
公开(公告)号：US08055828B2
公开(公告)日：2011-11-08
申请号：US13028440
申请日：2011-02-16
申请人： Gregory R. Conti , Franck Dahan
发明人： Gregory R. Conti , Franck Dahan
IPC分类号： G06F13/24 , G06F1/26
CPC分类号： G06F13/24 , Y02D10/14
摘要： An electronic power management system comprising plural processors operable in different security and context-related modes and having respective supply voltage inputs and clock inputs, said processors having at least one interrupt input and at least one wait for interrupt output. The system further comprises a power control circuit operable to configurably adjust supply voltages and clock rates for said supply voltage inputs and clock inputs. The system further comprises a wait for interrupt expansion circuit responsive to the at least one wait for interrupt output to provide an interrupt signal, at least one of said processors operable to configure said power control circuit in response to the interrupt signal.
摘要翻译：一种电子电源管理系统，包括可在不同安全性和上下文相关模式下操作的多个处理器，并且具有相应的电源电压输入和时钟输入，所述处理器具有至少一个中断输入和至少一个等待中断输出。该系统还包括功率控制电路，其可操作以可配置地调节所述电源电压输入和时钟输入的电源电压和时钟速率。所述系统还包括响应于所述至少一个等待中断输出以提供中断信号的等待中断扩展电路，所述处理器中的至少一个可操作以响应于所述中断信号配置所述功率控制电路。

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