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1. 发明授权

US08656112B2 Checkpointed tag prefetcher 失效
标题翻译：检查点标签预取器
公开(公告)号：US08656112B2
公开(公告)日：2014-02-18
申请号：US13610071
申请日：2012-09-11
申请人： Harold Wade Cain, III , Jong-Deok Choi
发明人： Harold Wade Cain, III , Jong-Deok Choi
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： A dual-mode prefetch system for implementing checkpoint tag prefetching includes: a data array for storing data fetched from cache memory; a set of cache tags identifying the data stored in the data array; a checkpoint tag array storing data identification information; and a cache controller with prefetch logic.
摘要翻译：用于实现检查点标签预取的双模预取系统包括：用于存储从高速缓冲存储器取出的数据的数据阵列; 一组标识存储在数据阵列中的数据的缓存标签; 存储数据识别信息的检查点标签阵列; 以及具有预取逻辑的缓存控制器。

2. 发明授权

US08572341B2 Overflow handling of speculative store buffers 失效
标题翻译：溢出处理推测性存储缓冲区
公开(公告)号：US08572341B2
公开(公告)日：2013-10-29
申请号：US12559615
申请日：2009-09-15
申请人： Colin B. Blundell , Harold Wade Cain, III , Gheorghe C. Cascaval , Maged Milad Michael
发明人： Colin B. Blundell , Harold Wade Cain, III , Gheorghe C. Cascaval , Maged Milad Michael
IPC分类号： G06F12/00
CPC分类号： G06F9/3842 , G06F9/3824
摘要： A method, a system and a computer program product for handling speculative stores. The system determines when a speculative store buffer is not full. An indicator is generated when the speculative store buffer is not full, and the speculative stores are input into the speculative store buffer. When the speculative store buffer is full, a full buffer indicator is generated. Speculative stores prevented from entering the speculative store buffer are overflow stores. The overflow list is searched to determine whether one or more addresses of the overflow stores are present in the overflow list. When one or more addresses of the overflow stores are not present in the overflow list, the overflow stores are stored in the overflow list.
摘要翻译：一种用于处理投机店的方法，系统和计算机程序产品。系统确定推测存储缓冲区何时未满。当推测存储缓冲区未满时，生成指示符，并将推测存储输入到推测存储缓冲区。当推测性存储缓冲区已满时，将生成完整的缓冲区指示符。防止进入推测存储缓冲区的推测存储是溢出存储。搜索溢出列表以确定溢出列表中是否存在溢出存储的一个或多个地址。当溢出列表中不存在溢出存储的一个或多个地址时，溢出存储将存储在溢出列表中。

3. 发明授权

US08972704B2 Code section optimization by removing memory barrier instruction and enclosing within a transaction that employs hardware transaction memory 有权
标题翻译：通过删除内存障碍指令并将其包含在采用硬件事务内存的事务中进行代码段优化
公开(公告)号：US08972704B2
公开(公告)日：2015-03-03
申请号：US13326320
申请日：2011-12-15
申请人： Toshihiko Koju , Takuya Nakaike , Ali Ijaz Sheikh , Harold Wade Cain, III , Maged M. Michael
发明人： Toshihiko Koju , Takuya Nakaike , Ali Ijaz Sheikh , Harold Wade Cain, III , Maged M. Michael
IPC分类号： G06F9/52 , G06F9/30 , G06F9/46 , G06F9/38
CPC分类号： G06F9/522 , G06F8/4441 , G06F8/458 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3851 , G06F9/466 , G06F9/467 , G06F11/3409 , G06F11/3466 , G06F2201/81 , G06F2201/865 , G06F2201/88
摘要： A code section of a computer program to be executed by a computing device includes memory barrier instructions. Where the code section satisfies a threshold, the code section is modified, by enclosing the code section within a transaction that employs hardware transactional memory of the computing device, and removing the memory barrier instructions from the code section. Execution of the code section as has been enclosed within the transaction can be monitored to yield monitoring results. Where the monitoring results satisfy an abort threshold corresponding to excessive aborting of the execution of the code section as has been enclosed within the transaction, the code section is split into code sub-sections, and each code sub-section enclosed within a separate transaction that employs the hardware transactional memory. Splitting the code section sections and enclosing each code sub-section within a separate transaction can decrease occurrence of the code section aborting during execution.
摘要翻译：由计算设备执行的计算机程序的代码部分包括存储器障碍指令。在代码部分满足阈值的情况下，通过将代码部分包围在使用计算设备的硬件事务存储器的事务中，并从代码部分移除存储器障碍指令来修改代码部分。可以监视执行代码部分的内容，以便产生监视结果。如果监视结果满足对应于已经包含在交易内的代码段的执行的过度中止所对应的中止阈值，则代码部分被分割为代码子部分，并且每个代码子部分包含在单独的交易中，采用硬件事务内存。拆分代码段部分并在单独的事务中包围每个代码子部分可以减少代码段在执行期间中止的发生。

4. 发明申请

US20140075124A1 Selective Delaying of Write Requests in Hardware Transactional Memory Systems 审中-公开
公开(公告)号：US20140075124A1
公开(公告)日：2014-03-13
申请号：US13606973
申请日：2012-09-07
申请人： Colin B. Blundell , Harold Wade Cain, III , Jose Eduardo Moreira
发明人： Colin B. Blundell , Harold Wade Cain, III , Jose Eduardo Moreira
IPC分类号： G06F12/08
CPC分类号： G06F9/467
摘要： Techniques for conflict detection in hardware transactional memory (HTM) are provided. In one aspect, a method for detecting conflicts in HTM includes the following steps. Conflict detection is performed eagerly by setting read and write bits in a cache as transactions having read and write requests are made. A given one of the transactions is stalled when a conflict is detected whereby more than one of the transactions are accessing data in the cache in a conflicting way. An address of the conflicting data is placed in a predictor. The predictor is queried whenever the write requests are made to determine whether they correspond to entries in the predictor. A copy of the data corresponding to entries in the predictor is placed in a store buffer. The write bits in the cache are set and the copy of the data in the store buffer is merged in at transaction commit.

5. 发明申请

US20120303857A1 Checkpointed Tag Prefetcher 有权
标题翻译：检查点标签预取器
公开(公告)号：US20120303857A1
公开(公告)日：2012-11-29
申请号：US13564829
申请日：2012-08-02
申请人： Harold Wade Cain, III , Jong-Deok Choi
发明人： Harold Wade Cain, III , Jong-Deok Choi
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： A cache management method using checkpoint tags in checkpoint mode includes steps of: receiving a request to save data; fetching at least one cache block including the data from cache memory; writing the data from the at least one cache block into the data array; writing a physical address and metadata of the cache block into an array of cache memory tags; and upon receipt of a restore request: fetching an identifier for the at least one cache block stored in the checkpoint tag array; reloading the cache memory with the at least one cache block in the checkpoint tag array; and switching to normal mode.
摘要翻译：在检查点模式中使用检查点标签的高速缓存管理方法包括以下步骤：接收保存数据的请求; 从高速缓冲存储器中取出包含数据的至少一个缓存块; 将来自所述至少一个高速缓存块的数据写入所述数据阵列; 将高速缓存块的物理地址和元数据写入高速缓存存储器标签阵列; 并且在接收到恢复请求时：获取存储在所述检查点标签阵列中的所述至少一个高速缓存块的标识符; 使用所述检查点标签阵列中的所述至少一个高速缓存块重新加载所述高速缓冲存储器; 并切换到正常模式。

6. 发明授权

US08131894B2 Method and system for a sharing buffer 有权
标题翻译：共享缓冲区的方法和系统
公开(公告)号：US08131894B2
公开(公告)日：2012-03-06
申请号：US12623496
申请日：2009-11-23
申请人： Harold Wade Cain, III , Rui Hou , Xiaowei Shen , Huayong Wang
发明人： Harold Wade Cain, III , Rui Hou , Xiaowei Shen , Huayong Wang
IPC分类号： G06F13/12
CPC分类号： G06F9/30087 , G06F9/467 , G06F9/5016
摘要： A system, method, and computer readable article of manufacture for sharing buffer management. The system includes: a predictor module to predict at runtime a transaction data size of a transaction according to history information of the transaction; and a resource management module to allocate sharing buffer resources for the transaction according to the predicted transaction data size in response to beginning of the transaction, to record an actual sharing buffer size occupied by the transaction in response to the successful commitment of the transaction, and to update the history information of the transaction.
摘要翻译：用于共享缓冲区管理的系统，方法和计算机可读制造品。该系统包括：预测器模块，用于根据交易的历史信息在运行时预测交易的交易数据大小; 以及资源管理模块，用于响应于所述事务的开始，根据预测的事务数据大小来分配所述事务的共享缓冲器资源，以响应所述事务的成功承诺来记录所述事务所占用的实际共享缓冲区大小;以及更新交易的历史信息。

7. 发明授权

US07818722B2 Computer implemented method and system for accurate, efficient and adaptive calling context profiling 失效
标题翻译：计算机实现的方法和系统，用于准确，高效和自适应的调用上下文分析
公开(公告)号：US07818722B2
公开(公告)日：2010-10-19
申请号：US11450656
申请日：2006-06-09
申请人： Harold Wade Cain, III , Jong-Deok Choi , Mauricio Jose Serrano , Xiaotong Zhuang
发明人： Harold Wade Cain, III , Jong-Deok Choi , Mauricio Jose Serrano , Xiaotong Zhuang
IPC分类号： G06F9/44
CPC分类号： G06F11/3466 , G06F2201/865
摘要： Computer implemented method, system and computer usable program code for profiling the execution of an application that is both space- and time-efficient and highly accurate. A computer implemented method for profiling the execution of an application includes sampling execution characteristics of the application at a plurality of sampling points to provide samples, and deriving a calling context of the samples. The application is continuously executed between sampling points while additional profiling data is gathered.
摘要翻译：计算机实现的方法，系统和计算机可用程序代码，用于分析空间和时间高效且高度准确的应用程序的执行。用于分析应用的执行的计算机实现的方法包括在多个采样点处对应用的采样执行特性，以提供采样，以及导出样本的呼叫上下文。应用程序在采样点之间持续执行，同时收集附加的分析数据。

8. 发明申请

US20080263257A1 Checkpointed Tag Prefetcher 有权
标题翻译：检查点标签预取器
公开(公告)号：US20080263257A1
公开(公告)日：2008-10-23
申请号：US11736548
申请日：2007-04-17
申请人： Harold Wade Cain III , Jong-Deok Choi
发明人： Harold Wade Cain III , Jong-Deok Choi
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： A dual-mode prefetch mechanism for implementing checkpoint tag prefetching includes: a data array for storing data fetched from cache memory; a set of cache tags for identifying the data stored in the data array; a set of checkpoint tags for storing data identification; a cache controller including prefetch logic, the prefetch logic including a checkpoint prefetch controller and a checkpoint prefetch operator.
摘要翻译：用于实现检查点标签预取的双模式预取机制包括：用于存储从高速缓冲存储器取出的数据的数据阵列; 用于识别存储在数据阵列中的数据的一组缓存标签; 一组用于存储数据识别的检查点标签; 包括预取逻辑的高速缓存控制器，预取逻辑包括检查点预取控制器和检查点预取操作符。

9. 发明申请

US20130007374A1 Checkpointed Tag Prefetcher 失效
标题翻译：检查点标签预取器
公开(公告)号：US20130007374A1
公开(公告)日：2013-01-03
申请号：US13610071
申请日：2012-09-11
申请人： Harold Wade Cain, III , Jong-Deok Choi
发明人： Harold Wade Cain, III , Jong-Deok Choi
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： A dual-mode prefetch system for implementing checkpoint tag prefetching includes: a data array for storing data fetched from cache memory; a set of cache tags identifying the data stored in the data array; a checkpoint tag array storing data identification information; and a cache controller with prefetch logic.
摘要翻译：用于实现检查点标签预取的双模预取系统包括：用于存储从高速缓冲存储器取出的数据的数据阵列; 一组标识存储在数据阵列中的数据的缓存标签; 存储数据识别信息的检查点标签阵列; 以及具有预取逻辑的缓存控制器。

10. 发明申请

US20080288926A1 Computer Implemented Method and System for Accurate, Efficient and Adaptive Calling Context Profiling 失效
标题翻译：计算机实现方法和系统，用于精确，高效和自适应的调用上下文分析
公开(公告)号：US20080288926A1
公开(公告)日：2008-11-20
申请号：US12141222
申请日：2008-06-18
申请人： Harold Wade Cain, III , Jong-Deok Choi , Mauricio Jose Serrano , Xiaotong Zhuang
发明人： Harold Wade Cain, III , Jong-Deok Choi , Mauricio Jose Serrano , Xiaotong Zhuang
IPC分类号： G06F9/44
CPC分类号： G06F11/3466 , G06F2201/865
摘要： Computer implemented method, system and computer usable program code for profiling the execution of an application that is both space-and time-efficient and highly accurate. A computer implemented method for profiling the execution of an application includes sampling execution characteristics of the application at a plurality of sampling points to provide samples, and deriving a calling context of the samples. The application is continuously executed between sampling points while additional profiling data is gathered.
摘要翻译：计算机实现的方法，系统和计算机可用程序代码，用于分析空间和时间高效且高度准确的应用程序的执行。用于分析应用的执行的计算机实现的方法包括在多个采样点处对应用的采样执行特性，以提供采样，以及导出样本的呼叫上下文。应用程序在采样点之间持续执行，同时收集附加的分析数据。

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