专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08370533B2 Executing flash storage access requests 有权
标题翻译：执行闪存访问请求
公开(公告)号：US08370533B2
公开(公告)日：2013-02-05
申请号：US13345410
申请日：2012-01-06
申请人： Pranay Koka , Michael Oliver McCracken , Herbert Dewitt Schwetman, Jr. , Jan Lodewijk Bonebakker
发明人： Pranay Koka , Michael Oliver McCracken , Herbert Dewitt Schwetman, Jr. , Jan Lodewijk Bonebakker
IPC分类号： G06F13/00
CPC分类号： G06F12/0246 , G06F12/08 , G06F12/0802 , G06F12/0866 , G06F12/10 , G06F13/28 , G06F2212/2022 , G06F2212/214
摘要： A system includes multiple nodes coupled using a network of processor buses. The multiple nodes include a first processor node, including one or more processing cores and main memory, and a flash memory node coupled to the first processor node via a first processor bus of the network of processor buses. The flash memory node includes a flash memory including flash pages, a first memory including a cache partition for storing cached flash pages for the flash pages in the flash memory and a control partition for storing cache control data and contexts of requests to access the flash pages, and a logic module including a direct memory access (DMA) register and configured to receive a first request from the first processor node via the first processor bus to access the flash pages.
摘要翻译：系统包括使用处理器总线网络耦合的多个节点。多个节点包括第一处理器节点，包括一个或多个处理核心和主存储器，以及经由处理器总线网络的第一处理器总线耦合到第一处理器节点的闪存节点。闪速存储器节点包括闪速存储器，其包括闪存页，第一存储器，其包括用于存储闪速存储器中的闪存页的高速缓存闪存页的高速缓存分区;以及用于存储高速缓存控制数据的控制分区和访问闪存页的请求的上下文以及包括直接存储器访问（DMA）寄存器并被配置为经由第一处理器总线从第一处理器节点接收第一请求以访问闪存页的逻辑模块。

2. 发明授权

US08280251B2 Data transmission using direct and indirect optical paths 有权
标题翻译：使用直接和间接光路的数据传输
公开(公告)号：US08280251B2
公开(公告)日：2012-10-02
申请号：US12426844
申请日：2009-04-20
申请人： Pranay Koka , Herbert Dewitt Schwetman, Jr. , Xuezhe Zheng
发明人： Pranay Koka , Herbert Dewitt Schwetman, Jr. , Xuezhe Zheng
IPC分类号： H04J14/00
CPC分类号： H04J14/0278 , H04J14/0267
摘要： A system for transmitting data, including: a transmitter node having a setup path packet and multiple data packets; a receiver node connected to the transmitter node by a first optical channel (OC); and a first intermediate node having a first forwarding module and connected to the transmitter node by a second OC and to the receiver node by a third OC, where the transmitter node transmits the setup path packet and a first subset of the multiple data packets to the first intermediate node using the second OC, where the first forwarding module relays, in response to receiving the setup packet, the first subset to the receiver node by switching the first subset from the second OC to the third OC, and where the receiver node receives a second subset of the multiple data packets from the transmitter node using the first OC.
摘要翻译：一种用于发送数据的系统，包括：具有建立路径分组和多个数据分组的发射机节点; 通过第一光信道（OC）连接到发射机节点的接收机节点; 以及第一中间节点，其具有第一转发模块，并且由第二OC连接到所述发射机节点，并且由第三OC连接到所述接收机节点，其中所述发射机节点将所述建立路径分组和所述多个数据分组的第一子集发送到使用第二OC的第一中间节点，其中响应于接收到建立分组，第一转发模块通过将第一子集从第二OC切换到第三OC，以及接收方节点接收的第一子集，将第一子集中继到接收方节点来自使用第一OC的发射机节点的多个数据分组的第二子集。

3. 发明申请

US20110179208A1 TIME DIVISION MULTIPLEXING BASED ARBITRATION FOR SHARED OPTICAL LINKS 有权
标题翻译：时分多路复用基于共享光链路的仲裁
公开(公告)号：US20110179208A1
公开(公告)日：2011-07-21
申请号：US12688749
申请日：2010-01-15
申请人： Pranay Koka , Michael Oliver McCracken , Herbert Dewitt Schwetman, JR. , Xuezhe Zheng , Ashok Krishnamoorthy
发明人： Pranay Koka , Michael Oliver McCracken , Herbert Dewitt Schwetman, JR. , Xuezhe Zheng , Ashok Krishnamoorthy
IPC分类号： G06F13/372
CPC分类号： H04J3/1682 , G06F15/17381 , H04J14/08
摘要： A method for arbitration including selecting, for an arbitration interval corresponding to a timeslot, a sending node from a plurality of sending nodes in an arbitration domain, where the plurality of sending nodes include a plurality of source counters; broadcasting, by the sending node and in response to selecting the sending node, a transmitter arbitration request for the timeslot during the arbitration interval; receiving, by the plurality of sending nodes, the transmitter arbitration request; incrementing the plurality of source counters in response to receiving the transmitter arbitration request; and sending, during the timeslot, a data item from the sending node to a receiving node via an optical data channel.
摘要翻译：一种仲裁方法，包括从仲裁域中的多个发送节点中选择对应于时隙的仲裁间隔的发送节点，其中所述多个发送节点包括多个源计数器; 由发送节点广播并响应于选择发送节点在仲裁间隔期间对时隙的发射机仲裁请求; 由所述多个发送节点接收所述发射机仲裁请求; 响应于接收到发射机仲裁请求而递增所述多个源计数器; 以及在所述时隙期间经由光学数据信道从所述发送节点发送到接收节点的数据项。

4. 发明授权

US07571188B1 Cache abstraction for modeling database performance 有权
标题翻译：缓存抽象用于建模数据库性能
公开(公告)号：US07571188B1
公开(公告)日：2009-08-04
申请号：US10948389
申请日：2004-09-23
申请人： Herbert Dewitt Schwetman, Jr. , Philip Eugene Cannata
发明人： Herbert Dewitt Schwetman, Jr. , Philip Eugene Cannata
IPC分类号： G06F7/00 , G06F17/00
CPC分类号： G06F11/3447 , G06F11/3409 , G06F2201/80 , G06F2201/88 , G06F2201/885 , Y10S707/99945 , Y10S707/99948
摘要： A method for modeling a database management system involving receiving a query, computing a hit rate value associated with a cache, wherein the hit rate value is computed using a counter group, comparing the hit rate value to a predetermined value to obtain a result, providing a reply to the query if the result is a hit, incrementing a counter in the counter group when the cache is not full and proceeding to a next cache if the result is a miss, and providing a diagnostic output for the database management system.
摘要翻译：一种用于对数据库管理系统进行建模的方法，包括接收查询，计算与高速缓存相关联的命中率值，其中使用计数器组计算命中率值，将命中率值与预定值进行比较以获得结果，如果结果是命中，则对查询的回复，当缓存不满时递增计数器组中的计数器，并且如果结果为未命中则继续进行下一个缓存，并为数据库管理系统提供诊断输出。

5. 发明授权

US08291175B2 Processor-bus attached flash main-memory module 有权
标题翻译：处理器总线附带的闪存主内存模块
公开(公告)号：US08291175B2
公开(公告)日：2012-10-16
申请号：US12581073
申请日：2009-10-16
申请人： Pranay Koka , Michael Oliver McCracken , Herbert Dewitt Schwetman, Jr. , Jan Lodewijk Bonebakker
发明人： Pranay Koka , Michael Oliver McCracken , Herbert Dewitt Schwetman, Jr. , Jan Lodewijk Bonebakker
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0817 , G06F12/0246
摘要： A method for processing a read request identifying an address. The method includes receiving, at a module including a flash memory and a memory buffer, the read request from a requesting processor, mapping, using a coherence directory controller within the module, the address to a cache line in a cache memory associated with a remote processor, and sending a coherency message from the module to the remote processor to change a state of the cache line in the cache memory. The method further includes receiving, at the module, the cache line from the remote processor, sending, using processor bus and in response to the read request, the cache line to the requesting processor, identifying a requested page stored within the flash memory based on the address, storing a copy of the requested page in the memory buffer, and writing the cache line to the copy of the requested page.
摘要翻译：一种用于处理识别地址的读取请求的方法。该方法包括在包括闪速存储器和存储器缓冲器的模块处接收来自请求处理器的读取请求，使用模块内的一致性目录控制器将与地址相关联的高速缓冲存储器中的高速缓存行的地址进行映射处理器，以及从所述模块向所述远程处理器发送一致性消息以改变所述高速缓冲存储器中的所述高速缓存行的状态。该方法还包括在模块处接收来自远程处理器的高速缓存行，使用处理器总线和响应于读取请求向请求处理器发送高速缓存行，基于所述地址将所请求的页面的副本存储在所述存储器缓冲器中，以及将所述高速缓存行写入所请求的页面的副本。

6. 发明申请

US20120110251A1 PROCESSOR-BUS-CONNECTED FLASH STORAGE MODULE 有权
标题翻译：处理器总线连接的闪存存储模块
公开(公告)号：US20120110251A1
公开(公告)日：2012-05-03
申请号：US13345410
申请日：2012-01-06
申请人： Pranay Koka , Michael Oliver McCracken , Herbert Dewitt Schwetman, JR. , Jan Lodewijk Bonebakker
发明人： Pranay Koka , Michael Oliver McCracken , Herbert Dewitt Schwetman, JR. , Jan Lodewijk Bonebakker
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/08 , G06F12/0802 , G06F12/0866 , G06F12/10 , G06F13/28 , G06F2212/2022 , G06F2212/214
摘要： A system includes multiple nodes coupled using a network of processor buses. The multiple nodes include a first processor node, including one or more processing cores and main memory, and a flash memory node coupled to the first processor node via a first processor bus of the network of processor buses. The flash memory node includes a flash memory including flash pages, a first memory including a cache partition for storing cached flash pages for the flash pages in the flash memory and a control partition for storing cache control data and contexts of requests to access the flash pages, and a logic module including a direct memory access (DMA) register and configured to receive a first request from the first processor node via the first processor bus to access the flash pages.
摘要翻译：系统包括使用处理器总线网络耦合的多个节点。多个节点包括第一处理器节点，包括一个或多个处理核心和主存储器，以及经由处理器总线网络的第一处理器总线耦合到第一处理器节点的闪存节点。闪速存储器节点包括闪速存储器，其包括闪存页，第一存储器，其包括用于存储闪速存储器中的闪存页的高速缓存闪存页的高速缓存分区;以及用于存储高速缓存控制数据的控制分区和访问闪存页的请求的上下文以及包括直接存储器访问（DMA）寄存器并被配置为经由第一处理器总线从第一处理器节点接收第一请求以访问闪存页的逻辑模块。

7. 发明申请

US20110082965A1 PROCESSOR-BUS-CONNECTED FLASH STORAGE MODULE 有权
标题翻译：处理器总线连接的闪存存储模块
公开(公告)号：US20110082965A1
公开(公告)日：2011-04-07
申请号：US12572189
申请日：2009-10-01
申请人： Pranay Koka , Michael Oliver McCracken , Herbert Dewitt Schwetman, JR. , Jan Lodewijk Bonebakker
发明人： Pranay Koka , Michael Oliver McCracken , Herbert Dewitt Schwetman, JR. , Jan Lodewijk Bonebakker
IPC分类号： G06F12/00 , G06F13/28 , G06F12/02
CPC分类号： G06F12/0246 , G06F12/08 , G06F12/0802 , G06F12/0866 , G06F12/10 , G06F13/28 , G06F2212/2022 , G06F2212/214
摘要： A system includes multiple nodes coupled using a network of processor buses. The multiple nodes include a first processor node, including one or more processing cores and main memory, and a flash memory node coupled to the first processor node via a first processor bus of the network of processor buses. The flash memory node includes a flash memory including flash pages, a first memory including a cache partition for storing cached flash pages for the flash pages in the flash memory and a control partition for storing cache control data and contexts of requests to access the flash pages, and a logic module including a direct memory access (DMA) register and configured to receive a first request from the first processor node via the first processor bus to access the flash pages.
摘要翻译：系统包括使用处理器总线网络耦合的多个节点。多个节点包括第一处理器节点，包括一个或多个处理核心和主存储器，以及经由处理器总线网络的第一处理器总线耦合到第一处理器节点的闪存节点。闪速存储器节点包括闪速存储器，其包括闪存页，第一存储器，其包括用于存储闪速存储器中的闪存页的高速缓存闪存页的高速缓存分区;以及用于存储高速缓存控制数据的控制分区和访问闪存页的请求的上下文以及包括直接存储器访问（DMA）寄存器并被配置为经由第一处理器总线从第一处理器节点接收第一请求以访问闪存页的逻辑模块。

8. 发明授权

US08824496B2 Two-phase arbitration mechanism for shared optical links 有权
标题翻译：共享光链路的两相仲裁机制
公开(公告)号：US08824496B2
公开(公告)日：2014-09-02
申请号：US12610124
申请日：2009-10-30
申请人： Pranay Koka , Michael Oliver McCracken , Herbert Dewitt Schwetman, Jr. , Xuezhe Zheng , Ashok Krishnamoorthy
发明人： Pranay Koka , Michael Oliver McCracken , Herbert Dewitt Schwetman, Jr. , Xuezhe Zheng , Ashok Krishnamoorthy
IPC分类号： H04L12/43
CPC分类号： H04J14/0256 , H04J14/0204 , H04J14/0205 , H04J14/0212 , H04J14/0267 , H04Q2213/1301
摘要： A method for arbitration in an arbitration domain. The method includes: receiving, by each node of a plurality of nodes in the arbitration domain, an arbitration request from each sending node of the plurality of nodes in the arbitration domain, where the plurality of nodes in the arbitration domain each use a shared data channel to send data to a set of receiving nodes; assigning, by each node in the arbitration domain, consecutive time slots to each sending node based on a plurality of priorities assigned to the plurality of nodes in the arbitration domain; for each time slot: sending, from the arbitration domain, a switch request to a receiving node designated by the sending node, where the receiving node is in the set of receiving nodes; and sending, by the sending node, data to the receiving node via the shared data channel during the time slot.
摘要翻译：仲裁域仲裁的方法。该方法包括：由仲裁域中的多个节点的每个节点接收来自仲裁域中的多个节点的每个发送节点的仲裁请求，其中仲裁域中的多个节点都使用共享数据通道将数据发送到一组接收节点; 基于分配给仲裁域中的多个节点的多个优先级，将仲裁域中的每个节点分配给每个发送节点的连续时隙; 对于每个时隙：从所述仲裁域发送切换请求到由所述发送节点指定的接收节点，其中所述接收节点在所述接收节点集合中; 并且在该时隙期间，由发送节点将数据经由共享数据信道发送到接收节点。

9. 发明授权

US08285140B2 Shared-source-row optical data channel organization for a switched arbitrated on-chip optical network 有权
标题翻译：用于交换仲裁的片上光网络的共享源行光数据信道组织
公开(公告)号：US08285140B2
公开(公告)日：2012-10-09
申请号：US12723591
申请日：2010-03-12
申请人： Michael Oliver McCracken , Pranay Koka , Herbert Dewitt Schwetman, Jr. , Xuezhe Zheng , Ashok Krishnamoorthy
发明人： Michael Oliver McCracken , Pranay Koka , Herbert Dewitt Schwetman, Jr. , Xuezhe Zheng , Ashok Krishnamoorthy
IPC分类号： H04J14/00
CPC分类号： H04Q11/0062 , H04Q11/0005 , H04Q2011/005 , H04Q2011/0058 , H04Q2011/0064
摘要： A system including first and second sending nodes, a horizontal optical data link (ODL) having optical signals propagating in opposite directions in first and second waveguide segments, a vertical ODL having optical signals propagating in the same direction throughout third and fourth waveguide segments, a first optical output switch operatively connecting the first sending node and the first waveguide segment and configured to switch first data item onto the first waveguide segment during a first timeslot, a second optical output switch operatively connecting the second sending node and the second waveguide segment and configured to switch second data item onto the second waveguide segment during a second timeslot, and an optical coupler pair operatively connecting the first and second waveguide segments to the third and fourth waveguide segments, respectively, and redirecting the first and the second data items from the horizontal to the vertical ODL.
摘要翻译：一种包括第一和第二发送节点的系统，具有在第一和第二波导段中以相反方向传播的光信号的水平光数据链路（ODL），具有沿相同方向在第三和第四波导段传播的光信号的垂直ODL，第一光输出开关，其可操作地连接第一发送节点和第一波导段，并且被配置为在第一时隙期间将第一数据项切换到第一波导段上;第二光输出开关，可操作地连接第二发送节点和第二波导段，在第二时隙期间将第二数据项切换到第二波导段上，以及光耦合器对，将第一和第二波导段分别可操作地连接到第三和第四波导段，并将第一和第二数据项从水平方向重定向到垂直ODL。

10. 发明授权

US08176220B2 Processor-bus-connected flash storage nodes with caching to support concurrent DMA accesses from multiple processors 有权
标题翻译：处理器总线连接的具有缓存的闪存存储节点，以支持来自多个处理器的并发DMA访问
公开(公告)号：US08176220B2
公开(公告)日：2012-05-08
申请号：US12572189
申请日：2009-10-01
申请人： Pranay Koka , Michael Oliver McCracken , Herbert Dewitt Schwetman, Jr. , Jan Lodewijk Bonebakker
发明人： Pranay Koka , Michael Oliver McCracken , Herbert Dewitt Schwetman, Jr. , Jan Lodewijk Bonebakker
IPC分类号： G06F13/00
CPC分类号： G06F12/0246 , G06F12/08 , G06F12/0802 , G06F12/0866 , G06F12/10 , G06F13/28 , G06F2212/2022 , G06F2212/214
摘要： A system includes multiple nodes coupled using a network of processor buses. The multiple nodes include a first processor node, including one or more processing cores and main memory, and a flash memory node coupled to the first processor node via a first processor bus of the network of processor buses. The flash memory node includes a flash memory including flash pages, a first memory including a cache partition for storing cached flash pages for the flash pages in the flash memory and a control partition for storing cache control data and contexts of requests to access the flash pages, and a logic module including a direct memory access (DMA) register and configured to receive a first request from the first processor node via the first processor bus to access the flash pages.
摘要翻译：系统包括使用处理器总线网络耦合的多个节点。多个节点包括第一处理器节点，包括一个或多个处理核心和主存储器，以及经由处理器总线网络的第一处理器总线耦合到第一处理器节点的闪存节点。闪速存储器节点包括闪速存储器，其包括闪存页，第一存储器，其包括用于存储闪速存储器中的闪存页的高速缓存闪存页的高速缓存分区;以及用于存储高速缓存控制数据的控制分区和访问闪存页的请求的上下文以及包括直接存储器访问（DMA）寄存器并被配置为经由第一处理器总线从第一处理器节点接收第一请求以访问闪存页的逻辑模块。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式