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    • 2. 发明申请
    • AMPLIFYING CIRCUIT
    • 放大电路
    • US20090140811A1
    • 2009-06-04
    • US12274015
    • 2008-11-19
    • Kenichi MIYAMOTOHiroaki ISHII
    • Kenichi MIYAMOTOHiroaki ISHII
    • H03F3/26
    • H03F3/303G09G3/3685H03F2200/297
    • First and second voltage buffers are added to an amplifying circuit including input and output amplifying stages in which a P-MOS transistor and an N-MOS transistor operate as a push-pull circuit. An input of the first voltage buffer is connected to an output of the amplifying circuit, and an output of the first voltage buffer is connected via a first phase compensating capacitor to a gate electrode of the P-MOS transistor, and is connected via a second phase compensating capacitor to a gate electrode of the N-MOS transistor. An input of the second voltage buffer is connected to the output of the amplifying circuit, and an output of the second voltage buffer is connected via a third phase compensating capacitor to the gate electrode of the P-MOS transistor, and is connected via a fourth phase compensating capacitor to the gate electrode of the N-MOS transistor.
    • 将第一和第二电压缓冲器加到包括P-MOS晶体管和N-MOS晶体管作为推挽电路工作的输入和输出放大级的放大电路中。 第一电压缓冲器的输入端连接到放大电路的输出,第一电压缓冲器的输出经由第一相位补偿电容器连接到P-MOS晶体管的栅电极,并经由第二电压缓冲器 相位补偿电容器到N-MOS晶体管的栅电极。 第二电压缓冲器的输入端连接到放大电路的输出端,第二电压缓冲器的输出经由第三相位补偿电容器连接到P-MOS晶体管的栅电极,并通过第四电压缓冲器 N相MOS晶体管的栅电极相位补偿电容。
    • 3. 发明申请
    • Non-halogen series floor material
    • 非卤素系列地板材料
    • US20050095412A1
    • 2005-05-05
    • US10695450
    • 2003-10-29
    • Eiji SakaguchiMakoto KoyamaJunichi TakedaYoshiharu NishinoHiroaki Ishii
    • Eiji SakaguchiMakoto KoyamaJunichi TakedaYoshiharu NishinoHiroaki Ishii
    • B32B5/30B32B7/02E04F15/16B32B1/00B32B27/32
    • B32B27/20B32B5/30B32B7/02B32B25/10B32B27/32B32B2309/105B32B2323/10B32B2419/04E04F15/16Y10T428/2495Y10T428/24975Y10T428/26Y10T428/263Y10T428/266Y10T428/268Y10T428/269Y10T442/3886Y10T442/678Y10T442/699
    • A non-halogen series floor material includes a first intermediate resin layer containing filler of 100 to 400 mass parts with respect to resin ingredient of 100 mass parts, the resin ingredient consisting essentially of resin having no chlorine atom in chemical structure, a surface resin layer integrally formed at an upper surface side of the first intermediate resin layer, the surface resin layer containing resin having no chloride atom in chemical structure and having a thickness of 100 to 1,000 μm, a second intermediate resin layer integrally formed at a lower surface side of the first intermediate resin layer, the second intermediate resin layer containing resin having no chloride atom in chemical structure and filler of 0 to 200 mass parts with respect to resin ingredient of 100 mass parts, and a backing layer integrally formed at a lower surface side of the second intermediate resin layer, the backing layer being formed of a fibrous fabric constituted by fibers containing resin having no chloride atom in chemical structure. A content ratio of the filler in the second intermediate resin layer with respect to the resin ingredient thereof is smaller than a content ratio of the filler in the first intermediate resin layer with respect to the resin ingredient thereof. A thickness of the second intermediate resin layer is 100 μm or more. A thickness of the second intermediate resin layer is 50% or less of a total thickness of three resin layers.
    • 非卤素系列地板材料包括相对于100质量份的树脂成分含有100〜400质量份的填料的第一中间树脂层,所述树脂成分基本上由化学结构中没有氯原子的树脂组成,表面树脂层 一体地形成在第一中间树脂层的上表面侧,表面树脂层含有化学结构中没有氯原子的树脂,其厚度为100-1000μm,在第一中间树脂层的下表面一体形成的第二中间树脂层 第一中间树脂层,含有化学结构中不含氯原子的树脂的第二中间树脂层和相对于100质量份的树脂成分为0〜200质量份的填料,以及在第一中间树脂层的下表面侧一体形成的背衬层 第二中间树脂层,背衬层由由含树脂的纤维构成的纤维织物形成 化学结构中没有氯原子。 第二中间树脂层中的填料相对于树脂成分的含有率小于第一中间树脂层中的填料相对于树脂成分的含有比例。 第二中间树脂层的厚度为100μm以上。 第二中间树脂层的厚度为三层树脂层的总厚度的50%以下。
    • 8. 发明申请
    • MAGNETIC TAPE LIBRARY DEVICE
    • 磁带图书馆设备
    • US20100270186A1
    • 2010-10-28
    • US12765035
    • 2010-04-22
    • HIROAKI ISHII
    • HIROAKI ISHII
    • B65D85/00
    • G11B15/6885
    • To provide a magnetic tape library device with which a plurality of housed magazines can be extracted safely from the device with the same operation, while the device is made to be simple. The magnetic tape library device includes: a plurality of magazines for housing a plurality of magnetic tape cartridges inside thereof; a device main body for housing the magazines within a same plane in a freely movable manner and in series in an inserting/extracting direction from an inserting/extracting slot; a connecting mechanism for enabling the plurality of magazines to be connected with each other or to be released by a releasing operation from outside; and a locking mechanism for enabling at least the magazine on the back side of the inserting/extracting direction of the device main body, among the plurality of magazines, to be locked or to be released from the locked state at the inserting/extracting slot side.
    • 为了提供一种磁带库装置,通过该磁带库装置,可以以相同的操作从装置中安全地提取多个收纳的杂志,同时使装置简单。 磁带库装置包括:多个用于在其内容纳多个磁带盒的杂志; 装置主体,用于以可自由移动的方式在相同的平面内容纳所述杂志,并从插入/取出槽沿插入/取出方向串联; 连接机构,用于使多个箱体能够彼此连接或通过外部的释放操作而被释放; 以及锁定机构,用于使多个箱中的装置主体的插入/取出方向的后侧上的至少能够在插入/取出槽侧被锁定或从锁定状态解除 。
    • 9. 发明授权
    • Amplifying circuit
    • 放大电路
    • US07724089B2
    • 2010-05-25
    • US12274015
    • 2008-11-19
    • Kenichi MiyamotoHiroaki Ishii
    • Kenichi MiyamotoHiroaki Ishii
    • H03F3/45
    • H03F3/303G09G3/3685H03F2200/297
    • First and second voltage buffers are added to an amplifying circuit including input and output amplifying stages in which a P-MOS transistor and an N-MOS transistor operate as a push-pull circuit. An input of the first voltage buffer is connected to an output of the amplifying circuit, and an output of the first voltage buffer is connected via a first phase compensating capacitor to a gate electrode of the P-MOS transistor, and is connected via a second phase compensating capacitor to a gate electrode of the N-MOS transistor. An input of the second voltage buffer is connected to the output of the amplifying circuit, and an output of the second voltage buffer is connected via a third phase compensating capacitor to the gate electrode of the P-MOS transistor, and is connected via a fourth phase compensating capacitor to the gate electrode of the N-MOS transistor.
    • 将第一和第二电压缓冲器加到包括P-MOS晶体管和N-MOS晶体管作为推挽电路工作的输入和输出放大级的放大电路中。 第一电压缓冲器的输入端连接到放大电路的输出,第一电压缓冲器的输出经由第一相位补偿电容器连接到P-MOS晶体管的栅电极,并经由第二电压缓冲器 相位补偿电容器到N-MOS晶体管的栅电极。 第二电压缓冲器的输入端连接到放大电路的输出端,第二电压缓冲器的输出经由第三相位补偿电容器连接到P-MOS晶体管的栅电极,并通过第四电压缓冲器 N相MOS晶体管的栅电极相位补偿电容。