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1. 发明授权

US07869262B2 Memory device with an asymmetric layout structure 有权
标题翻译：具有非对称布局结构的内存设备
公开(公告)号：US07869262B2
公开(公告)日：2011-01-11
申请号：US11699089
申请日：2007-01-29
申请人： Huai-Ying Huang
发明人： Huai-Ying Huang
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： An SRAM device includes a first inverter; a second inverter cross-coupled with the first inverter; a first pass gate transistor connecting the first inverter to a bit line; and a second pass gate transistor connecting the second inverter to a complementary bit line, wherein the first or second pass gate transistor has a layout structure where a first distance between its gate conductive layer and its source contact is purposefully designed to be substantially different from a second distance between its gate conductive layer and its drain contact for reducing leakage current induced by misalignment of the gate conductive layer with respect to the source contact.
摘要翻译： SRAM装置包括第一反相器; 与所述第一反相器交叉耦合的第二反相器; 将第一反相器连接到位线的第一通路栅极晶体管; 以及将所述第二反相器连接到互补位线的第二通栅晶体管，其中所述第一或第二栅极晶体管具有布置结构，其栅极导电层与其源极接触之间的第一距离被有目的地设计为与其栅极导电层和漏极接触之间的第二距离，用于减小由栅极导电层相对于源极接触不对准而引起的漏电流。

2. 发明授权

US07535751B2 Dual-port SRAM device 有权
标题翻译：双端口SRAM器件
公开(公告)号：US07535751B2
公开(公告)日：2009-05-19
申请号：US11705281
申请日：2007-02-12
申请人： Huai-Ying Huang , Forst Hung , Feng-Ming Chang
发明人： Huai-Ying Huang , Forst Hung , Feng-Ming Chang
IPC分类号： G11C11/00 , G11C8/00
CPC分类号： G11C11/412
摘要： A dual-port SRAM cell structure includes a first inverter area where a first inverter is constructed on a semiconductor substrate; a second inverter area where a second inverter is constructed on the semiconductor substrate, the first and second inverters being cross-coupled to form one or more data stage nodes for latching a value; and a first pass gate transistor area where a first write port pass gate transistor and a first read port pass gate transistor share a first oxide defined region for balancing device performances thereof. The first write port pass gate transistor and the first read port pass gate transistor are coupled to the data storage nodes for selectively reading or writing a value therefrom or thereinto.
摘要翻译：双端口SRAM单元结构包括在半导体衬底上构造第一反相器的第一反相器区域; 第二反相器区域，其中在所述半导体衬底上构造第二反相器，所述第一和第二反相器交叉耦合以形成用于锁存值的一个或多个数据级节点; 以及第一写入口通过栅极晶体管和第一读取端口通过栅极晶体管的第一通过栅极晶体管区域共享用于平衡器件性能的第一氧化物限定区域。第一写入口通过栅极晶体管和第一读出端口通过栅极晶体管耦合到数据存储节点，用于选择性地读取或写入其值。

3. 发明授权

US08441829B2 Stable SRAM cell 有权
公开(公告)号：US08441829B2
公开(公告)日：2013-05-14
申请号：US12727985
申请日：2010-03-19
申请人： Huai-Ying Huang , Yu-Kuan Lin , Sheng Chiang Hung , Feng-Ming Chang , Jui-Lin Chen , Ping-Wei Wang
发明人： Huai-Ying Huang , Yu-Kuan Lin , Sheng Chiang Hung , Feng-Ming Chang , Jui-Lin Chen , Ping-Wei Wang
IPC分类号： G11C15/00
CPC分类号： G11C11/412 , G11C11/419
摘要： SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.

4. 发明申请

US20110198699A1 INTEGRATED SEMICONDUCTOR STRUCTURE FOR SRAM AND FABRICATION METHODS THEREOF 有权
标题翻译：用于SRAM及其制造方法的集成半导体结构
公开(公告)号：US20110198699A1
公开(公告)日：2011-08-18
申请号：US12706809
申请日：2010-02-17
申请人： Sheng Chiang Hung , Huai-Ying Huang , Ping-Wei Wang
发明人： Sheng Chiang Hung , Huai-Ying Huang , Ping-Wei Wang
IPC分类号： H01L27/092
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L27/11 , H01L29/495 , H01L29/4966 , H01L29/66545 , H01L29/7848
摘要： A SRAM device with metal gate transistors is provided. The SRAM device includes a PMOS structure and an NMOS structure over a substrate. Each of the PMOS and the NMOS structure includes a p-type metallic work function layer and an n-type metallic work function layer. The p-type work metallic function layer and the n-type metallic work function layer form a combined work function for the PMOS and the NMOS structures.
摘要翻译：提供了具有金属栅极晶体管的SRAM器件。 SRAM器件在衬底上包括PMOS结构和NMOS结构。 PMOS和NMOS结构中的每一个包括p型金属功函数层和n型金属功函数层。 p型工作金属功能层和n型金属功函数层形成PMOS和NMOS结构的组合功函数。

5. 发明授权

US08940589B2 Well implant through dummy gate oxide in gate-last process 有权
标题翻译：通过伪栅极氧化物在栅极 - 最后工艺中注入
公开(公告)号：US08940589B2
公开(公告)日：2015-01-27
申请号：US12789780
申请日：2010-05-28
申请人： Sheng Chiang Hung , Huai-Ying Huang , Ping-Wei Wang
发明人： Sheng Chiang Hung , Huai-Ying Huang , Ping-Wei Wang
IPC分类号： H01L21/84 , H01L29/66 , H01L21/8238
CPC分类号： H01L29/7836 , H01L21/823807 , H01L21/823892 , H01L29/0847 , H01L29/167 , H01L29/495 , H01L29/4966 , H01L29/66545 , H01L29/6659
摘要： The present disclosure relates to methods for fabricating a field-effect transistor. The method includes performing a pocket implantation to a semiconductor substrate; thereafter forming a polysilicon layer on the semiconductor substrate; and patterning the polysilicon layer to form a polysilicon gate.The field-effect transistor (FET) includes a well of a first type dopant, formed in a semiconductor substrate; a metal gate disposed on the semiconductor substrate and overlying the well; a channel formed in the semiconductor substrate and underlying the metal gate; source and drain regions of a second type dopant opposite from the first type, the source and drain regions being formed in the semiconductor substrate and on opposite sides of the channel; and a pocket doping profile of the first type dopant and being defined in the well to form a continuous and uniform doping region from the source region to the drain region.
摘要翻译：本公开涉及用于制造场效应晶体管的方法。该方法包括对半导体衬底进行袋注入; 然后在半导体衬底上形成多晶硅层; 并构图多晶硅层以形成多晶硅栅极。场效应晶体管（FET）包括形成在半导体衬底中的第一类型掺杂剂的阱; 设置在半导体衬底上并覆盖阱的金属栅极; 形成在半导体衬底中并在金属栅极下方的沟道; 源极和漏极区域形成在半导体衬底中并在沟道的相对侧上;第二类型掺杂物的源极和漏极区域与第一类型相反，以及第一类型掺杂剂的口袋掺杂分布，并且在阱中限定以形成从源极区域到漏极区域的连续且均匀的掺杂区域。

6. 发明申请

US20110241127A1 Well implant through dummy gate oxide in gate-last process 有权
标题翻译：通过伪栅极氧化物在栅极 - 最后工艺中注入
公开(公告)号：US20110241127A1
公开(公告)日：2011-10-06
申请号：US12789780
申请日：2010-05-28
申请人： Sheng Chiang Hung , Huai-Ying Huang , Ping-Wei Wang
发明人： Sheng Chiang Hung , Huai-Ying Huang , Ping-Wei Wang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7836 , H01L21/823807 , H01L21/823892 , H01L29/0847 , H01L29/167 , H01L29/495 , H01L29/4966 , H01L29/66545 , H01L29/6659
摘要： The present disclosure relates to methods for fabricating a field-effect transistor. The method includes performing a pocket implantation to a semiconductor substrate; thereafter forming a polysilicon layer on the semiconductor substrate; and patterning the polysilicon layer to form a polysilicon gate.The field-effect transistor (FET) includes a well of a first type dopant, formed in a semiconductor substrate; a metal gate disposed on the semiconductor substrate and overlying the well; a channel formed in the semiconductor substrate and underlying the metal gate; source and drain regions of a second type dopant opposite from the first type, the source and drain regions being formed in the semiconductor substrate and on opposite sides of the channel; and a pocket doping profile of the first type dopant and being defined in the well to form a continuous and uniform doping region from the source region to the drain region.
摘要翻译：本公开涉及用于制造场效应晶体管的方法。该方法包括对半导体衬底进行袋注入; 然后在半导体衬底上形成多晶硅层; 并构图多晶硅层以形成多晶硅栅极。场效应晶体管（FET）包括形成在半导体衬底中的第一类型掺杂剂的阱; 设置在半导体衬底上并覆盖阱的金属栅极; 形成在半导体衬底中并在金属栅极下方的沟道; 源极和漏极区域形成在半导体衬底中并在沟道的相对侧上;第二类型掺杂物的源极和漏极区域与第一类型相反，以及第一类型掺杂剂的口袋掺杂分布，并且在阱中限定以形成从源极区域到漏极区域的连续且均匀的掺杂区域。

7. 发明申请

US20100315862A1 Stable SRAM Cell 有权
标题翻译：稳定的SRAM单元
公开(公告)号：US20100315862A1
公开(公告)日：2010-12-16
申请号：US12727985
申请日：2010-03-19
申请人： Huai-Ying Huang , Yu-Kuan Lin , Sheng Chiang Hung , Feng-Ming Chang , Jui-Lin Chen , Ping-Wei Wang
发明人： Huai-Ying Huang , Yu-Kuan Lin , Sheng Chiang Hung , Feng-Ming Chang , Jui-Lin Chen , Ping-Wei Wang
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C11/419
摘要： SRAM cells and SRAM cell arrays are described. In one embodiment, an SRAM cell includes a first inverter and a second inverter cross-coupled with the first inverter to form a first data storage node and a complimentary second data storage node for latching a value. The SRAM cell further includes a first pass-gate transistor and a switch transistor. A first source/drain of the first pass-gate transistor is coupled to the first data storage node, and a second source/drain of the first pass-gate transistor is coupled to a first bit line. The first source/drain of the switch transistor is coupled to the gate of the first pass-gate transistor.
摘要翻译：描述SRAM单元和SRAM单元阵列。在一个实施例中，SRAM单元包括与第一反相器交叉耦合的第一反相器和第二反相器，以形成第一数据存储节点和用于锁存值的互补的第二数据存储节点。 SRAM单元还包括第一栅极晶体管和开关晶体管。第一栅极晶体管的第一源极/漏极耦合到第一数据存储节点，并且第一栅极晶体管的第二源极/漏极耦合到第一位线。开关晶体管的第一源极/漏极耦合到第一通过栅极晶体管的栅极。

8. 发明授权

US07773407B2 8T low leakage SRAM cell 有权
标题翻译： 8T低泄漏SRAM单元
公开(公告)号：US07773407B2
公开(公告)日：2010-08-10
申请号：US12147400
申请日：2008-06-26
申请人： Huai-Ying Huang , Yu-Kuan Lin , Sheng Chiang Hung , Ping-Wei Wang
发明人： Huai-Ying Huang , Yu-Kuan Lin , Sheng Chiang Hung , Ping-Wei Wang
IPC分类号： G11C7/00
CPC分类号： G11C8/16 , G11C11/412
摘要： This invention discloses a static random access memory (SRAM) cell comprising a pair of cross-coupled inverters connected between a positive supply voltage (Vcc) and a first node, a first NMOS transistor with a gate and drain connected to the first node and a source connected to a ground, and a second NMOS transistor with a drain and source connected to the first node and the ground, respectively, and a gate connected to a control-line.
摘要翻译：本发明公开了一种静态随机存取存储器（SRAM）单元，其包括连接在正电源电压（Vcc）和第一节点之间的一对交叉耦合的反相器，具有与第一节点连接的栅极和漏极的第一NMOS晶体管和源极连接到地，以及第二NMOS晶体管，其漏极和源极分别连接到第一节点和地，以及栅极连接到控制线。

9. 发明申请

US20090323401A1 8T LOW LEAKAGE SRAM CELL 有权
标题翻译： 8T低漏电SRAM单元
公开(公告)号：US20090323401A1
公开(公告)日：2009-12-31
申请号：US12147400
申请日：2008-06-26
申请人： Huai-Ying Huang , Yu-Kuan Lin , Sheng Chiang Hung , Ping-Wei Wang
发明人： Huai-Ying Huang , Yu-Kuan Lin , Sheng Chiang Hung , Ping-Wei Wang
IPC分类号： G11C11/00
CPC分类号： G11C8/16 , G11C11/412
摘要： This invention discloses a static random access memory (SRAM) cell comprising a pair of cross-coupled inverters connected between a positive supply voltage (Vcc) and a first node, a first NMOS transistor with a gate and drain connected to the first node and a source connected to a ground, and a second NMOS transistor with a drain and source connected to the first node and the ground, respectively, and a gate connected to a control-line.
摘要翻译：本发明公开了一种静态随机存取存储器（SRAM）单元，其包括连接在正电源电压（Vcc）和第一节点之间的一对交叉耦合的反相器，具有与第一节点连接的栅极和漏极的第一NMOS晶体管和源极连接到地，以及第二NMOS晶体管，其漏极和源极分别连接到第一节点和地，以及栅极连接到控制线。

10. 发明申请

US20080180980A1 Memory device with an asymmetric layout structure 有权
标题翻译：具有非对称布局结构的内存设备
公开(公告)号：US20080180980A1
公开(公告)日：2008-07-31
申请号：US11699089
申请日：2007-01-29
申请人： Huai-Ying Huang
发明人： Huai-Ying Huang
IPC分类号： G11C5/02
CPC分类号： G11C11/412
摘要： An SRAM device includes a first inverter; a second inverter cross-coupled with the first inverter; a first pass gate transistor connecting the first inverter to a bit line; and a second pass gate transistor connecting the second inverter to a complementary bit line, wherein the first or second pass gate transistor has a layout structure where a first distance between its gate conductive layer and its source contact is purposefully designed to be substantially different from a second distance between its gate conductive layer and its drain contact for reducing leakage current induced by misalignment of the gate conductive layer with respect to the source contact.
摘要翻译： SRAM装置包括第一反相器; 与所述第一反相器交叉耦合的第二反相器; 将第一反相器连接到位线的第一通路栅极晶体管; 以及将所述第二反相器连接到互补位线的第二通栅晶体管，其中所述第一或第二栅极晶体管具有其栅极导电层与其源极接触之间的第一距离被有目的地设计为与其栅极导电层和漏极接触之间的第二距离，用于减小由栅极导电层相对于源极接触不对准而引起的漏电流。

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