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    • 3. 发明申请
    • Pre-Colored Methodology of Multiple Patterning
    • 多种图案预色彩方法
    • US20130263066A1
    • 2013-10-03
    • US13607946
    • 2012-09-10
    • Yen-Huei ChenHung-Jen LiaoJonathan Tsung-Yung Chang
    • Yen-Huei ChenHung-Jen LiaoJonathan Tsung-Yung Chang
    • G06F17/50
    • G06F17/5072G06F17/5068G06F2217/12Y02P90/265
    • Some embodiments relate to a method of pre-coloring word lines and control lines within an SRAM integrated chip design to avoid timing delays that result from processing variations introduced through multiple patterning lithography processes. The method is performed by generating a graphical IC layout file having an SRAM circuit with a plurality of word lines and Y-control lines. The word lines and Y-control lines are assigned a color during decomposition. The word lines and Y-control lines are further pre-colored in a manner that deliberately assigns the pre-colored data to a same mask. Therefore, during mask building, data associated with pre-colored word and Y-control lines is sent to a same mask, regardless of the colors that are assigned to the data. By assigning word and Y-control lines to a same mask through pre-coloring, processing variations between the word and Y-control lines are minimized, thereby mitigating timing variations in an SRAM circuit.
    • 一些实施例涉及在SRAM集成芯片设计中预先着色字线和控制线的方法,以避免由通过多次图案化光刻工艺引入的处理变化而产生的定时延迟。 该方法通过生成具有多个字线和Y控制线的SRAM电路的图形IC布局文件来执行。 在分解过程中,字线和Y控制线被分配一个颜色。 字线和Y控制线进一步预先着色,以故意将预色数据分配给相同的掩码。 因此,在面具构建期间,与预色彩字和Y控制线相关联的数据被发送到相同的掩码,而不管分配给数据的颜色如何。 通过预分色将字和Y控制线分配给相同的掩码,字和Y控制线之间的处理变化被最小化,从而减轻SRAM电路中的定时变化。
    • 4. 发明申请
    • MEMORY CIRCUIT AND METHOD OF WRITING DATUM TO MEMORY CIRCUIT
    • 存储器电路和将数据写入存储器电路的方法
    • US20130188433A1
    • 2013-07-25
    • US13354884
    • 2012-01-20
    • Chih-Yu LINWei Min CHANYen-Huei CHENHung-Jen LIAOJonathan Tsung-Yung CHANG
    • Chih-Yu LINWei Min CHANYen-Huei CHENHung-Jen LIAOJonathan Tsung-Yung CHANG
    • G11C7/00
    • G11C11/419
    • A circuit includes a first node, a second node, a memory cell, a first data line, a second data line, and a write driver. The memory cell is coupled to the first node and the second node and powered by a first voltage at the first node and a second voltage at the second node. The first data line and the second data line are coupled to the memory cell. The write driver has a third node carrying a third voltage less than the first voltage during a write operation. The write deriver is coupled to the first data line and the second data line and configured to, during a write operation, selectively coupling one of the first data line and the second data line to the third node and coupling the other one of the first data line and the second data line to the first node.
    • 电路包括第一节点,第二节点,存储器单元,第一数据线,第二数据线和写驱动器。 存储器单元耦合到第一节点和第二节点,并由第一节点处的第一电压和第二节点处的第二电压供电。 第一数据线和第二数据线耦合到存储器单元。 写入驱动器具有在写入操作期间承载小于第一电压的第三电压的第三节点。 写引导器耦合到第一数据线和第二数据线,并且被配置为在写操作期间,选择性地将第一数据线和第二数据线之一耦合到第三节点,并将第一数据中的另一个耦合 线和第二条数据线到第一个节点。
    • 9. 发明授权
    • SRAM bit cell
    • SRAM位单元
    • US08363454B2
    • 2013-01-29
    • US13015773
    • 2011-01-28
    • Ping WangHung-Jen LiaoYen-Huei ChenJihi-Yu LinShao-Yu Chou
    • Ping WangHung-Jen LiaoYen-Huei ChenJihi-Yu LinShao-Yu Chou
    • G11C11/00
    • G11C11/412
    • A semiconductor memory bit cell includes an inverter latch including a pair of cross-coupled inverters. A first transistor has a gate coupled to a first control line and a source coupled to the inverter latch, and a second transistor has a gate coupled to a second control line and a drain coupled to the drain of the first transistor at a first node. A third transistor has a source coupled to the first node and a gate coupled to a word line, and a fourth transistor has a gate coupled to a source of the second transistor and to the inverter latch. A fifth transistor has a gate coupled to the word line and a drain coupled to a read bit line.
    • 半导体存储器位单元包括具有一对交叉耦合的反相器的反相器锁存器。 第一晶体管具有耦合到第一控制线的栅极和耦合到反相器锁存器的源极,并且第二晶体管具有耦合到第二控制线的栅极和在第一节点耦合到第一晶体管的漏极的漏极。 第三晶体管具有耦合到第一节点的源极和耦合到字线的栅极,并且第四晶体管具有耦合到第二晶体管的源极和反相器锁存器的栅极。 第五晶体管具有耦合到字线的栅极和耦合到读位线的漏极。