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1. 发明申请

US20130286330A1 OPTICAL FILM AND LIQUID CRYSTAL DISPLAY INCLUDING THE SAME 审中-公开
标题翻译：光学膜和液晶显示器，包括它们
公开(公告)号：US20130286330A1
公开(公告)日：2013-10-31
申请号：US13931835
申请日：2013-06-29
申请人： Moon-Yeon LEE , Hyeon CHO , Hyun-Gi KIM , Hae-Ryong CHUNG , Jong-Gyu LA
发明人： Moon-Yeon LEE , Hyeon CHO , Hyun-Gi KIM , Hae-Ryong CHUNG , Jong-Gyu LA
IPC分类号： G02F1/13363 , G02B1/08 , G02B5/30
CPC分类号： G02B5/3083 , C08F222/08 , C08L35/06 , G02B1/04 , G02B1/08 , G02B5/32 , G02B27/281 , G02F1/13363 , G02F1/133634 , G02F2202/40 , G02F2413/02 , Y10T428/1036
摘要： An optical film and a liquid crystal display including the same, the optical film including a first compensation layer having a relation of n1z>n1x>n1y between indexes of refraction n1x, n1y, and n1z in x-axis, y-axis, and z-axis directions on a plane; and a second compensation layer having a relation of n2x>n2y>n2z between indexes of refraction n2x, n2y, and n2z in x-axis, y-axis, and z-axis directions on a plane.
摘要翻译：一种光学膜和包括该光学膜的液晶显示器，所述光学膜包括具有x轴，y轴和z的折射率n1x，n1y和n1z之间的n1z> n1x> n1y的关系的第一补偿层在飞机上的方向; 以及在平面上的x轴，y轴和z轴方向上的折射指数n2x，n2y和n2z之间具有n2x> n2y> n2z的关系的第二补偿层。

2. 发明授权

US08304824B2 Semiconductor device comprising buried word lines 有权
标题翻译：包括掩埋字线的半导体器件
公开(公告)号：US08304824B2
公开(公告)日：2012-11-06
申请号：US12719493
申请日：2010-03-08
申请人： Hui-Jung Kim , Yong-Chul Oh , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
发明人： Hui-Jung Kim , Yong-Chul Oh , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L27/10891 , H01L27/0207 , H01L27/10817 , H01L27/10885 , H01L29/4236
摘要： A semiconductor device includes: an isolation layer for defining a plurality of active areas of a substrate, where the isolation layer is disposed on the substrate; a plurality of buried word lines having upper surfaces that are lower than the upper surfaces of the active areas, being surrounded by the active areas, and extending in a first direction parallel to a main surface of the substrate; a gate dielectric film interposed between the buried word lines and the active areas; and a plurality of buried bit lines having upper surfaces that are lower than the upper surfaces of the plurality of buried word lines and extending parallel to the main surface of the substrate in a second direction that differs from the first direction.
摘要翻译：半导体器件包括：用于限定衬底的多个有源区的隔离层，其中隔离层设置在衬底上; 具有比有源区域的上表面低的上表面的多个掩埋字线被有源区域包围，并且沿与基板的主表面平行的第一方向延伸; 介于掩埋字线和有源区之间的栅介质膜; 以及多个掩埋位线，其具有比所述多个掩埋字线的上表面低的上表面，并且在与所述第一方向不同的第二方向上平行于所述基板的主表面延伸。

3. 发明申请

US20120007208A1 Semiconductor Devices and Methods of Manufacturing the Same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120007208A1
公开(公告)日：2012-01-12
申请号：US13177128
申请日：2011-07-06
申请人： Hyun-Gi Kim , Yongchul Oh , Yoosang Hwang , Cheolho Baek , Hui-Jung Kim , Young-Seung Cho
发明人： Hyun-Gi Kim , Yongchul Oh , Yoosang Hwang , Cheolho Baek , Hui-Jung Kim , Young-Seung Cho
IPC分类号： H01L29/06 , H01L21/762
CPC分类号： H01L27/10885 , H01L21/3086 , H01L21/76224 , H01L27/10817 , H01L27/10876
摘要： Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may include first and second active patterns. The second active patterns may protrude from the first active patterns. The semiconductor devices may also include a device isolation pattern between each of the first active patterns. The semiconductor devices may further include a sidewall mask on the first active patterns and the second active patterns. The semiconductor devices may additionally include a buried conductive pattern on the device isolation pattern.
摘要翻译：提供半导体器件及其制造方法。半导体器件可以包括第一和第二有源图案。第二活动图案可以从第一活动图案突出。半导体器件还可以包括在每个第一有源图案之间的器件隔离图案。半导体器件还可以包括在第一有源图案和第二活动图案上的侧壁掩模。半导体器件还可以在器件隔离图案上包括掩埋导电图案。

4. 发明授权

US08053316B2 Method of fabricating vertical channel transistor 有权
标题翻译：制造垂直沟道晶体管的方法
公开(公告)号：US08053316B2
公开(公告)日：2011-11-08
申请号：US12953785
申请日：2010-11-24
申请人： Kang-Uk Kim , Yongchul Oh , Hui-Jung Kim , Hyun-Woo Chung , Hyun-Gi Kim
发明人： Kang-Uk Kim , Yongchul Oh , Hui-Jung Kim , Hyun-Woo Chung , Hyun-Gi Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10885 , H01L29/66666 , H01L29/7827
摘要： A method of fabricating a vertical channel transistor includes: forming a line type active pattern on a substrate so as to extend in a first horizontal direction; forming a vertical channel isolating the active pattern in a second horizontal direction intersecting the first horizontal direction and extending vertically on the substrate; forming a buried bit line extending in the first horizontal direction on the substrate; and forming a word line extending in the second horizontal direction along at least one side surface of the vertical channel.
摘要翻译：制造垂直沟道晶体管的方法包括：在衬底上形成线状有源图案，以沿第一水平方向延伸; 形成在与所述第一水平方向相交并在所述基板上垂直延伸的第二水平方向隔离所述有源图案的垂直通道; 形成在所述基板上沿所述第一水平方向延伸的掩埋位线; 以及沿所述垂直通道的至少一个侧表面在所述第二水平方向上形成字线。

5. 发明申请

US20110111568A1 METHODS OF FABRICATING VERTICAL CHANNEL TRANSISTORS 有权
标题翻译：制造垂直通道晶体管的方法
公开(公告)号：US20110111568A1
公开(公告)日：2011-05-12
申请号：US12906630
申请日：2010-10-18
申请人： Kang-Uk Kim , Hyun-Woo Chung , Youngchul Oh , Hui-Jung Kim , Hyun-Gi Kim
发明人： Kang-Uk Kim , Hyun-Woo Chung , Youngchul Oh , Hui-Jung Kim , Hyun-Gi Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/7827 , H01L21/2815 , H01L27/0207 , H01L27/10876 , H01L27/10885 , H01L29/0657 , H01L29/41741 , H01L29/42376 , H01L29/4238 , H01L29/66666
摘要： Methods of fabricating vertical channel transistors may include forming an active region on a substrate, patterning the active region to form vertical channels at sides of the active region, forming a buried bit line in the active region between the vertical channels, and forming a word line facing a side of the vertical channel.
摘要翻译：制造垂直沟道晶体管的方法可以包括在衬底上形成有源区域，图案化有源区域以在有源区域的侧面形成垂直沟道，在垂直沟道之间的有源区域中形成掩埋位线，并形成字线面向垂直通道的一侧。

6. 发明申请

US20090250736A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20090250736A1
公开(公告)日：2009-10-08
申请号：US12385433
申请日：2009-04-08
申请人： Jae-Man Yoon , Yong-Chul Oh , Hui-Jung Kim , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
发明人： Jae-Man Yoon , Yong-Chul Oh , Hui-Jung Kim , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
IPC分类号： H01L29/94 , H01L29/78
CPC分类号： H01L27/0688 , H01L21/8221
摘要： In a semiconductor device and associated methods, the semiconductor device includes a substrate, an insulation layer on the substrate, a conductive structure on the insulation layer, the conductive structure including at least one metal silicide film pattern, a semiconductor pattern on the conductive structure, the semiconductor pattern protruding upwardly from the conductive structure, a gate electrode at least partially enclosing the semiconductor pattern, the gate electrode being spaced apart from the conductive structure, a first impurity region at a lower portion of the semiconductor pattern, and a second impurity region at an upper portion of the semiconductor pattern.
摘要翻译：在半导体器件和相关方法中，半导体器件包括衬底，衬底上的绝缘层，绝缘层上的导电结构，导电结构包括至少一种金属硅化物膜图案，导电结构上的半导体图案，所述半导体图案从所述导电结构向上突出，栅电极至少部分地封装所述半导体图案，所述栅电极与所述导电结构间隔开，所述半导体图案的下部的第一杂质区域和所述第二杂质区域在半导体图案的上部。

7. 发明授权

US08283229B2 Methods of fabricating vertical channel transistors 有权
标题翻译：制造垂直沟道晶体管的方法
公开(公告)号：US08283229B2
公开(公告)日：2012-10-09
申请号：US12906630
申请日：2010-10-18
申请人： Kang-Uk Kim , Hyun-Woo Chung , Yongchul Oh , Hui-Jung Kim , Hyun-Gi Kim
发明人： Kang-Uk Kim , Hyun-Woo Chung , Yongchul Oh , Hui-Jung Kim , Hyun-Gi Kim
IPC分类号： H01L29/772
CPC分类号： H01L29/7827 , H01L21/2815 , H01L27/0207 , H01L27/10876 , H01L27/10885 , H01L29/0657 , H01L29/41741 , H01L29/42376 , H01L29/4238 , H01L29/66666
摘要： Methods of fabricating vertical channel transistors may include forming an active region on a substrate, patterning the active region to form vertical channels at sides of the active region, forming a buried bit line in the active region between the vertical channels, and forming a word line facing a side of the vertical channel.
摘要翻译：制造垂直沟道晶体管的方法可以包括在衬底上形成有源区域，图案化有源区域以在有源区域的侧面形成垂直沟道，在垂直沟道之间的有源区域中形成掩埋位线，并形成字线面向垂直通道的一侧。

8. 发明授权

US08274112B2 Semiconductor memory device having pillar structures 有权
标题翻译：具有柱结构的半导体存储器件
公开(公告)号：US08274112B2
公开(公告)日：2012-09-25
申请号：US12689258
申请日：2010-01-19
申请人： Hui-Jung Kim , Yong-Chul Oh , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
发明人： Hui-Jung Kim , Yong-Chul Oh , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
IPC分类号： H01L29/78
CPC分类号： H01L27/10808 , H01L27/10855 , H01L27/10873 , H01L27/10885
摘要： A semiconductor memory device includes first and second active pillar structures protruding at an upper part of a substrate, buried bit lines each extending in a first direction, and first gate patterns and second gate patterns each extending in a second direction. The first and second active pillar structures occupy odd-numbered and even-numbered rows, respectively. The first and the second active pillar structures also occupy even-numbered and odd-numbered columns, respectively. The columns of the second active pillar structures are offset in the second direction from the columns of the first active pillar structures. Each buried bit line is connected to lower portions of the first active pillar structures which occupy one of the even-numbered columns and to lower portions of the second active pillar structures which occupy an adjacent one of the odd-numbered columns.
摘要翻译：半导体存储器件包括在衬底的上部突出的第一和第二有源柱结构，每个沿第一方向延伸的掩埋位线以及分别沿第二方向延伸的第一栅极图案和第二栅极图案。第一和第二主动柱结构分别占据奇数和偶数行。第一和第二主动支柱结构也分别占据偶数和奇数列。第二有源柱结构的列在与第一有源柱结构的列相反的第二方向上偏移。每个埋置的位线连接到占据偶数列中的一个的第一有源柱结构的下部和占据奇数列中的相邻一个的第二有源支柱结构的下部。

9. 发明申请

US20110220977A1 SEMICONDUCTOR DEVICES WITH BURIED BIT LINES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES 有权
标题翻译：带有双绞线的半导体器件及制造半导体器件的方法
公开(公告)号：US20110220977A1
公开(公告)日：2011-09-15
申请号：US12760140
申请日：2010-04-14
申请人： Jae-Man Yoon , Hui-Jung Kim , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim , Yong-Chul Oh
发明人： Jae-Man Yoon , Hui-Jung Kim , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim , Yong-Chul Oh
IPC分类号： H01L27/108 , H01L21/8242 , H01L21/336
CPC分类号： H01L27/108 , H01L21/84 , H01L27/10817 , H01L27/10876 , H01L27/10894 , H01L27/1203 , H01L29/7833
摘要： A semiconductor device, comprising: a vertical pillar transistor (VPT) formed on a silicon-on-insulator (SOI) substrate, the VPT including a body that has a lower portion and an upper portion, a source/drain node disposed at an upper end portion of the upper portion of the body and a drain/source node disposed at the lower portion of the body; a buried bit line (BBL) formed continuously on sidewalls and an upper surface of the lower portion, the BBL includes metal sificide; and a word line that partially enclosing the upper portion of the body of the VPT, wherein the BBL extends along a first direction and the word line extends in a second direction substantially perpendicular to the first direction. An offset region is disposed immediately beneath the word line.
摘要翻译：一种半导体器件，包括：形成在绝缘体上硅（SOI））衬底上的垂直立柱晶体管（VPT），所述VPT包括具有下部和上部的主体，设置在上部的源极/漏极节点本体的上部的端部和设置在主体的下部的排水/源节点; 在侧壁和下部的上表面上连续形成的埋置位线（BBL），BBL包括金属微孔; 以及字线，其部分地包围VPT的主体的上部，其中，BBL沿着第一方向延伸，并且字线在基本上垂直于第一方向的第二方向上延伸。偏移区域设置在字线的正下方。

10. 发明授权

US07999309B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07999309B2
公开(公告)日：2011-08-16
申请号：US12385433
申请日：2009-04-08
申请人： Jae-Man Yoon , Yong-Chul Oh , Hui-Jung Kim , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
发明人： Jae-Man Yoon , Yong-Chul Oh , Hui-Jung Kim , Hyun-Woo Chung , Hyun-Gi Kim , Kang-Uk Kim
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/0688 , H01L21/8221
摘要： In a semiconductor device and associated methods, the semiconductor device includes a substrate, an insulation layer on the substrate, a conductive structure on the insulation layer, the conductive structure including at least one metal silicide film pattern, a semiconductor pattern on the conductive structure, the semiconductor pattern protruding upwardly from the conductive structure, a gate electrode at least partially enclosing the semiconductor pattern, the gate electrode being spaced apart from the conductive structure, a first impurity region at a lower portion of the semiconductor pattern, and a second impurity region at an upper portion of the semiconductor pattern.
摘要翻译：在半导体器件和相关方法中，半导体器件包括衬底，衬底上的绝缘层，绝缘层上的导电结构，导电结构包括至少一种金属硅化物膜图案，导电结构上的半导体图案，所述半导体图案从所述导电结构向上突出，栅电极至少部分地封装所述半导体图案，所述栅电极与所述导电结构间隔开，所述半导体图案的下部的第一杂质区域和所述第二杂质区域在半导体图案的上部。

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