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1. 发明授权

US07767540B2 Transistor having a channel with tensile strain and oriented along a crystallographic orientation with increased charge carrier mobility 有权
标题翻译：晶体管具有具有拉伸应变的通道并沿着具有增加的电荷载流子迁移率的晶体取向定向
公开(公告)号：US07767540B2
公开(公告)日：2010-08-03
申请号：US11567268
申请日：2006-12-06
申请人： Igor Peidous , Thorsten Kammler , Andy Wei
发明人： Igor Peidous , Thorsten Kammler , Andy Wei
IPC分类号： H01L21/76
CPC分类号： H01L29/7843 , H01L21/26506 , H01L29/51 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7848
摘要： By appropriately orienting the channel length direction with respect to the crystallographic characteristics of the silicon layer, the stress-inducing effects of strained silicon/carbon material may be significantly enhanced compared to conventional techniques. In one illustrative embodiment, the channel may be oriented along the direction for a (100) surface orientation, thereby providing an electron mobility increase of approximately a factor of four.
摘要翻译：通过相对于硅层的结晶特性适当地定向沟道长度方向，与常规技术相比，应变硅/碳材料的应力诱导效应可以显着提高。在一个说明性实施例中，通道可以沿着（100）表面取向沿着<100>方向取向，从而提供大约四分之一的电子迁移率增加。

2. 发明申请

US20100096698A1 STRESS ENHANCED TRANSISTOR 有权
标题翻译：应力增强晶体管
公开(公告)号：US20100096698A1
公开(公告)日：2010-04-22
申请号：US12644882
申请日：2009-12-22
申请人： Igor Peidous , Rohit Pal
发明人： Igor Peidous , Rohit Pal
IPC分类号： H01L29/78 , H01L29/06
CPC分类号： H01L29/78687 , H01L29/66553 , H01L29/66621 , H01L29/66628 , H01L29/66772 , H01L29/7848
摘要： Stress enhanced MOS transistors are provided. A semiconductor device is provided that comprises a semiconductor-on-insulator structure, a gate insulator layer, a source region, a drain region and a conductive gate overlying the gate insulator layer. The semiconductor-on-insulator structure comprises: a substrate, a semiconductor layer, and an insulating layer disposed between the substrate and the semiconductor layer. The semiconductor layer has a first surface, a second surface and a first region. The gate insulator layer overlies the first region, the conductive gate overlies the gate insulator layer, and the source region and the drain region overlie the first surface and comprise a strain-inducing epitaxial layer
摘要翻译：提供了应力增强型MOS晶体管。提供一种半导体器件，其包括绝缘体上半导体结构，栅极绝缘体层，源极区域，漏极区域和覆盖栅极绝缘体层的导电栅极。绝缘体上半导体结构包括：衬底，半导体层和设置在衬底和半导体层之间的绝缘层。半导体层具有第一表面，第二表面和第一区域。栅极绝缘体层覆盖第一区域，导电栅极覆盖栅极绝缘体层，源区域和漏极区域覆盖在第一表面上，并且包括应变诱导外延层

3. 发明授权

US07534689B2 Stress enhanced MOS transistor and methods for its fabrication 有权
标题翻译：应力增强型MOS晶体管及其制造方法
公开(公告)号：US07534689B2
公开(公告)日：2009-05-19
申请号：US11562209
申请日：2006-11-21
申请人： Rohit Pal , Igor Peidous , David Brown
发明人： Rohit Pal , Igor Peidous , David Brown
IPC分类号： H01L21/20
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/02639 , H01L21/823807 , H01L21/823814 , H01L29/045 , H01L29/165 , H01L29/66636
摘要： A stress enhanced MOS transistor and methods for its fabrication are provided. In one embodiment the method comprises forming a gate electrode overlying and defining a channel region in a monocrystalline semiconductor substrate. A trench having a side surface facing the channel region is etched into the monocrystalline semiconductor substrate adjacent the channel region. The trench is filled with a second monocrystalline semiconductor material having a first concentration of a substitutional atom and with a third monocrystalline semiconductor material having a second concentration of the substitutional atom. The second monocrystalline semiconductor material is epitaxially grown to have a wall thickness along the side surface sufficient to exert a greater stress on the channel region than the stress that would be exerted by a monocrystalline semiconductor material having the second concentration if the trench was filled by the third monocrystalline material alone.
摘要翻译：提供了一种应力增强型MOS晶体管及其制造方法。在一个实施例中，该方法包括形成覆盖并限定单晶半导体衬底中的沟道区的栅电极。具有面向通道区域的侧表面的沟槽被蚀刻到与沟道区域相邻的单晶半导体衬底中。沟槽填充有具有第一浓度的取代原子的第二单晶半导体材料和具有第二浓度取代原子的第三单晶半导体材料。第二单晶半导体材料被外延生长以具有沿着侧表面的壁厚，足以在沟道区域施加比由具有第二浓度的单晶半导体材料施加的应力更大的应力，如果沟槽由第三单晶材料。

4. 发明申请

US20080258175A1 STRESSED MOS DEVICE 有权
标题翻译：应力MOS器件
公开(公告)号：US20080258175A1
公开(公告)日：2008-10-23
申请号：US12166166
申请日：2008-07-01
申请人： Igor PEIDOUS , Linda R. BLACK , Frank WIRBELEIT
发明人： Igor PEIDOUS , Linda R. BLACK , Frank WIRBELEIT
IPC分类号： H01L29/778
CPC分类号： H01L29/66636 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L29/1054 , H01L29/165 , H01L29/6656 , H01L29/66772 , H01L29/7848 , H01L29/78654
摘要： A stressed MOS device is provided that includes a silicon substrate, a gate electrode and an epitaxial layer of stress inducing monocrystalline semiconductor material. The silicon substrate is characterized by a monocrystalline silicon lattice constant. The gate electrode overlies a silicon channel region at the surface of the silicon substrate. The epitaxial layer of stress inducing monocrystalline semiconductor material is grown in the silicon substrate. The epitaxial layer of stress inducing monocrystalline semiconductor material has a lattice constant greater than the monocrystalline silicon lattice constant, and extends under the silicon channel region.
摘要翻译：提供了一种应力MOS器件，其包括硅衬底，栅电极和应力诱导单晶半导体材料的外延层。硅衬底的特征在于单晶硅晶格常数。栅电极覆盖在硅衬底的表面处的硅沟道区域。在硅衬底中生长应力诱导单晶半导体材料的外延层。应力诱导单晶半导体材料的外延层具有大于单晶硅晶格常数的晶格常数，并且在硅沟道区下延伸。

5. 发明申请

US20080142835A1 STRESS ENHANCED TRANSISTOR AND METHODS FOR ITS FABRICATION 有权
标题翻译：应力增强晶体管及其制造方法
公开(公告)号：US20080142835A1
公开(公告)日：2008-06-19
申请号：US11611784
申请日：2006-12-15
申请人： Igor Peidous , Rohit Pal
发明人： Igor Peidous , Rohit Pal
IPC分类号： H01L29/778 , H01L21/336
CPC分类号： H01L29/78687 , H01L29/66553 , H01L29/66621 , H01L29/66628 , H01L29/66772 , H01L29/7848
摘要： A stress enhanced MOS transistor and methods for its fabrication are provided. A semiconductor-on-insulator structure is provided which includes a semiconductor layer having a first surface. A strain-inducing epitaxial layer is blanket deposited over the first surface, and can then be used to create a source region and a drain region which overlie the first surface.
摘要翻译：提供了一种应力增强型MOS晶体管及其制造方法。提供了一种绝缘体上半导体结构，其包括具有第一表面的半导体层。应变诱导外延层被覆盖地沉积在第一表面上，然后可用于产生覆盖在第一表面上的源极区域和漏极区域。

6. 发明申请

US20070032024A1 Methods for fabricating a stressed MOS device 有权
标题翻译：制造应力MOS器件的方法
公开(公告)号：US20070032024A1
公开(公告)日：2007-02-08
申请号：US11197046
申请日：2005-08-03
申请人： Igor Peidous , Mario Pelella
发明人： Igor Peidous , Mario Pelella
IPC分类号： H01L21/336
CPC分类号： H01L29/66628 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： A method for fabricating a stressed MOS device in and on a semiconductor substrate is provided. The method comprises the steps of forming a gate electrode overlying the semiconductor substrate and etching a first trench and a second trench in the semiconductor substrate, the first trench and the second trench formed in alignment with the gate electrode. A stress inducing material is selectively grown in the first trench and in the second trench and conductivity determining impurity ions are implanted into the stress inducing material to form a source region in the first trench and a drain region in the second trench. To preserve the stress induced in the substrate, a layer of mechanically hard material is deposited on the stress inducing material after the step of ion implanting.
摘要翻译：提供了一种在半导体衬底中及其上制造应力MOS器件的方法。该方法包括以下步骤：形成覆盖半导体衬底并蚀刻半导体衬底中的第一沟槽和第二沟槽的栅电极，第一沟槽和第二沟槽与栅电极对准形成。在第一沟槽和第二沟槽中选择性地生长应力诱导材料，并且将导电性确定杂质离子注入到应力诱导材料中，以在第一沟槽中形成源区，在第二沟中形成漏极区。为了保持在衬底中引起的应力，在离子注入步骤之后，将一层机械硬质材料沉积在应力诱导材料上。

7. 发明申请

US20190027397A1 HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE COMPRISING A CHARGE TRAPPING LAYER FORMED ON A SUBSTRATE WITH A ROUGH SURFACE 审中-公开
公开(公告)号：US20190027397A1
公开(公告)日：2019-01-24
申请号：US16077142
申请日：2017-01-31
申请人： Igor PEIDOUS , SUNEDISON SEMCONDUCTOR LIMITED
发明人： Igor Peidous , Andrew M. Jones , Srikanth Kommu , Gang Wang , Jeffrey L. Libbert
IPC分类号： H01L21/762 , H01L21/28 , H01L21/02
CPC分类号： H01L21/76254 , H01L21/0245 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/28176
摘要： A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and the front surface of the single crystal semiconductor handle substrate has a surface roughness of at least about 0.1 micrometers as measured according to the root mean square method over a surface area of at least 30 micrometers by 30 micrometers. The composite structure further comprises a charge trapping layer in contact with the front surface, the charge trapping layer comprising poly crystalline silicon, the poly crystalline silicon comprising grains having a plurality of crystal orientations; a dielectric layer in contact with the charge trapping layer; and a single crystal semiconductor device layer in contact with the dielectric layer.

8. 发明申请

US20160351437A1 HIGH RESISTIVITY SOI WAFERS AND A METHOD OF MANUFACTURING THEREOF 审中-公开
标题翻译：高电阻SOI波形及其制造方法
公开(公告)号：US20160351437A1
公开(公告)日：2016-12-01
申请号：US15112083
申请日：2014-12-29
申请人： Igor PEIDOUS , SUNEDISON SEMICONDUCTOR LIMITED
发明人： Igor Peidous , Srikanth Kommu , Gang Wang , Shawn George Thomas
IPC分类号： H01L21/762
CPC分类号： H01L21/76251 , H01L21/76254
摘要： A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of Si1-xGex, Si1-xCx, Si1-x-yGexSny, Si1-x-y-zGexSnyCz, Ge1-xSnx, group IIIA-nitrides, semiconductor oxides, and any combination thereof.
摘要翻译：提供了用于制造SOI结构的高电阻率单晶半导体手柄结构。手柄结构包括在处理衬底和掩埋氧化物层之间的中间半导体层。中间半导体层包括多晶，非晶，纳米晶体或单晶结构，并且包括选自Si1-xGex，Si1-xCx，Si1-x-yGexSny，Si1-xy-zGexSnyCz，Ge1-xSnx， IIIA-氮化物，半导体氧化物及其任何组合。

9. 发明申请

US20080242014A1 METHODS FOR FABRICATING SEMICONDUCTOR SUBSTRATES WITH SILICON REGIONS HAVING DIFFERENTIAL CRYSTALLOGRAPHIC ORIENTATIONS 失效
标题翻译：用于制造具有差异晶体取向的硅区域的半导体衬底的方法
公开(公告)号：US20080242014A1
公开(公告)日：2008-10-02
申请号：US11693890
申请日：2007-03-30
申请人： Igor PEIDOUS
发明人： Igor PEIDOUS
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/76251 , H01L21/823878 , H01L21/84
摘要： A method is provided for fabricating a differential semiconductor substrate. A first structure is provided which comprises a first semiconductor substrate including a first semiconductor region, and a first oxide layer overlying a surface of the first semiconductor substrate. The first semiconductor substrate has a first crystallographic orientation. A second structure is provided which includes a second semiconductor substrate comprising a first layer and a second layer, and a second oxide layer which overlies a surface of the first layer. The second semiconductor substrate has a second crystallographic orientation different than the first crystallographic orientation. The first layer includes a second semiconductor region. The first layer and the second oxide layer are removed from the second structure, and assembled to the first semiconductor substrate to form a composite structure. A bonded composite structure is then formed by exposing the composite structure to a temperature adequate to cause bonding of the first oxide layer and the second oxide layer. Portions of the bonded composite structure are removed to expose the first semiconductor region and the second semiconductor region and thereby form the differential semiconductor substrate.
摘要翻译：提供了一种用于制造差分半导体衬底的方法。提供了第一结构，其包括包括第一半导体区域的第一半导体衬底和覆盖在第一半导体衬底的表面上的第一氧化物层。第一半导体衬底具有第一晶体取向。提供了第二结构，其包括包括第一层和第二层的第二半导体衬底和覆盖在第一层的表面上的第二氧化物层。第二半导体衬底具有不同于第一晶体取向的第二晶体取向。第一层包括第二半导体区域。从第二结构移除第一层和第二氧化物层，并组装到第一半导体衬底以形成复合结构。然后通过将复合结构暴露于足以引起第一氧化物层和第二氧化物层的结合的温度来形成粘结复合结构。去除粘合复合结构的部分以露出第一半导体区域和第二半导体区域，从而形成差分半导体衬底。

10. 发明申请

US20080119031A1 STRESS ENHANCED MOS TRANSISTOR AND METHODS FOR ITS FABRICATION 有权
标题翻译：应力增强MOS晶体管及其制造方法
公开(公告)号：US20080119031A1
公开(公告)日：2008-05-22
申请号：US11562209
申请日：2006-11-21
申请人： Rohit Pal , Igor Peidous , David Brown
发明人： Rohit Pal , Igor Peidous , David Brown
IPC分类号： H01L21/20 , H01L21/36 , H01L31/20
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/02639 , H01L21/823807 , H01L21/823814 , H01L29/045 , H01L29/165 , H01L29/66636
摘要： A stress enhanced MOS transistor and methods for its fabrication are provided. In one embodiment the method comprises forming a gate electrode overlying and defining a channel region in a monocrystalline semiconductor substrate. A trench having a side surface facing the channel region is etched into the monocrystalline semiconductor substrate adjacent the channel region. The trench is filled with a second monocrystalline semiconductor material having a first concentration of a substitutional atom and with a third monocrystalline semiconductor material having a second concentration of the substitutional atom. The second monocrystalline semiconductor material is epitaxially grown to have a wall thickness along the side surface sufficient to exert a greater stress on the channel region than the stress that would be exerted by a monocrystalline semiconductor material having the second concentration if the trench was filled by the third monocrystalline material alone.
摘要翻译：提供了一种应力增强型MOS晶体管及其制造方法。在一个实施例中，该方法包括形成覆盖并限定单晶半导体衬底中的沟道区的栅电极。具有面向通道区域的侧表面的沟槽被蚀刻到与沟道区域相邻的单晶半导体衬底中。沟槽填充有具有第一浓度的取代原子的第二单晶半导体材料和具有第二浓度取代原子的第三单晶半导体材料。第二单晶半导体材料被外延生长以具有沿着侧表面的壁厚，足以在沟道区域施加比由具有第二浓度的单晶半导体材料施加的应力更大的应力，如果沟槽由第三单晶材料。

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