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1. 发明授权

US08078899B2 Asynchronous conversion circuitry apparatus, systems, and methods 有权
公开(公告)号：US08078899B2
公开(公告)日：2011-12-13
申请号：US13022843
申请日：2011-02-08
申请人： Rajit Manohar , Clinton W. Kelly , Virantha Ekanayake , Christopher LaFrieda , Hong Tam , Ilya Ganusov , Raymond Nijssen , Marcel Van der Goot
发明人： Rajit Manohar , Clinton W. Kelly , Virantha Ekanayake , Christopher LaFrieda , Hong Tam , Ilya Ganusov , Raymond Nijssen , Marcel Van der Goot
IPC分类号： G06F1/04 , H03K19/00 , H04L7/00
CPC分类号： G06F1/12
摘要： Apparatus, systems, and methods operate to receive a sufficient number of asynchronous input tokens at the inputs of an asynchronous apparatus to conduct a specified processing operation, some of the tokens decoded to determine an operation type associated with the specified processing operation; to receive an indication that outputs of the asynchronous apparatus are ready to conduct the specified processing operation; to signal a synchronous circuit to process data included in the tokens according to the specified processing operation; and to convert synchronous outputs from the synchronous circuit into asynchronous output tokens to be provided to outputs of the asynchronous apparatus when the synchronous outputs result from the specified processing operation. Additional apparatus, systems, and methods are disclosed.

2. 发明申请

US20220012012A1 Systems and Methods for Sparsity Operations in a Specialized Processing Block 有权
公开(公告)号：US20220012012A1
公开(公告)日：2022-01-13
申请号：US17485123
申请日：2021-09-24
申请人： Martin Langhammer , Michael Wu , Nihat Engin Tunali , Ilya Ganusov
发明人： Martin Langhammer , Michael Wu , Nihat Engin Tunali , Ilya Ganusov
IPC分类号： G06F7/523 , G06F7/50
摘要： This disclosure is directed to a digital signal processing (DSP) block that includes multiple weight registers configurable to receive and store a first plurality of values, and multiple multipliers that are each configurable to receive a respective value of the first plurality of values. The DSP block further includes one or more inputs configurable to receive a second plurality of values, and a multiplexer network configurable to receive the second plurality of values and route each respective value of the second plurality of values to a multiplier of the multipliers. The multipliers are configurable to simultaneously multiply each value of the first plurality of values by a respective value of the second plurality of values to generate a plurality of products. Additionally, the DSP block includes adder circuitry configurable to generate a first sum and a second sum based on the plurality of products.

3. 发明申请

US20110130171A1 ASYNCHRONOUS CONVERSION CIRCUITRY APPARATUS, SYSTEMS, AND METHODS 有权
公开(公告)号：US20110130171A1
公开(公告)日：2011-06-02
申请号：US13022843
申请日：2011-02-08
申请人： Rajit Manohar , Clinton W. Kelly , Virantha Ekanayake , Christopher LaFrieda , Hong Tam , Ilya Ganusov , Raymond Nijssen , Marcel Van der Goot
发明人： Rajit Manohar , Clinton W. Kelly , Virantha Ekanayake , Christopher LaFrieda , Hong Tam , Ilya Ganusov , Raymond Nijssen , Marcel Van der Goot
IPC分类号： G06F1/04 , G06F1/12 , H03K19/177 , H04W88/02
CPC分类号： G06F1/12
摘要： Apparatus, systems, and methods operate to receive a sufficient number of asynchronous input tokens at the inputs of an asynchronous apparatus to conduct a specified processing operation, some of the tokens decoded to determine an operation type associated with the specified processing operation; to receive an indication that outputs of the asynchronous apparatus are ready to conduct the specified processing operation; to signal a synchronous circuit to process data included in the tokens according to the specified processing operation; and to convert synchronous outputs from the synchronous circuit into asynchronous output tokens to be provided to outputs of the asynchronous apparatus when the synchronous outputs result from the specified processing operation. Additional apparatus, systems, and methods are disclosed.

4. 发明申请

US20110062987A1 ASYNCHRONOUS CONVERSION CIRCUITRY APPARATUS, SYSTEMS, AND METHODS 有权
标题翻译：异步转换电路设备，系统和方法
公开(公告)号：US20110062987A1
公开(公告)日：2011-03-17
申请号：US12559069
申请日：2009-09-14
申请人： Rajit Manohar , Clinton W. Kelly , Virantha Ekanayake , Christopher LaFrieda , Hong Tam , Ilya Ganusov , Raymond Nijssen , Marcel Van der Goot
发明人： Rajit Manohar , Clinton W. Kelly , Virantha Ekanayake , Christopher LaFrieda , Hong Tam , Ilya Ganusov , Raymond Nijssen , Marcel Van der Goot
IPC分类号： H03K19/177 , H03K19/00
CPC分类号： G06F1/12
摘要： Apparatus, systems, and methods operate to receive a sufficient number of asynchronous input tokens at the inputs of an asynchronous apparatus to conduct a specified processing operation, some of the tokens decoded to determine an operation type associated with the specified processing operation; to receive an indication that outputs of the asynchronous apparatus are ready to conduct the specified processing operation; to signal a synchronous circuit to process data included in the tokens according to the specified processing operation; and to convert synchronous outputs from the synchronous circuit into asynchronous output tokens to be provided to outputs of the asynchronous apparatus when the synchronous outputs result from the specified processing operation. Additional apparatus, systems, and methods are disclosed.
摘要翻译：装置，系统和方法操作以在异步装置的输入处接收足够数量的异步输入令牌以进行指定的处理操作，解码的一些令牌以确定与指定的处理操作相关联的操作类型; 以接收异步装置的输出准备好进行指定的处理操作的指示; 根据指定的处理操作，向同步电路发信号处理令牌中包含的数据; 并且当从指定的处理操作产生同步输出时，将来自同步电路的同步输出转换为异步输出令牌，以提供给异步装置的输出。公开了附加装置，系统和方法。

5. 发明授权

US07730263B2 Future execution prefetching technique and architecture 有权
标题翻译：未来执行预取技术和架构
公开(公告)号：US07730263B2
公开(公告)日：2010-06-01
申请号：US11335829
申请日：2006-01-20
申请人： Martin Burtscher , Ilya Ganusov
发明人： Martin Burtscher , Ilya Ganusov
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F9/3851 , G06F9/30047 , G06F9/3017 , G06F9/3455 , G06F9/3832 , G06F12/0862
摘要： A prefetching technique referred to as future execution (FE) dynamically creates a prefetching thread for each active thread in a processor by simply sending a copy of all committed, register-writing instructions in a primary thread to an otherwise idle processor. On the way to the second processor, a value predictor replaces each predictable instruction with a load immediate instruction, where the immediate is the predicted result that the instruction is likely to produce during its nth next dynamic execution. Executing this modified instruction stream (i.e., the prefetching thread) in another processor allows computation of the future results of the instructions that are not directly predictable. This causes the issuance of prefetches into the shared memory hierarchy, thereby reducing the primary thread's memory access time and speeding up the primary thread's execution.
摘要翻译：称为未来执行（FE）的预取技术通过简单地将主线程中的所有提交的寄存器写入指令的副本发送到另外空闲的处理器来动态地为处理器中的每个活动线程创建预取线程。在到第二处理器的途中，值预测器用负载立即指令替换每个可预测指令，其中立即数是指令在其第n次下一次动态执行期间可能产生的预测结果。在另一个处理器中执行该修改的指令流（即，预取线程）允许计算未直接预测的指令的未来结果。这将导致预取到共享内存层次结构中，从而减少主线程的内存访问时间并加快主线程的执行速度。

6. 发明申请

US20070174555A1 Future execution prefetching technique and architecture 有权
标题翻译：未来执行预取技术和架构
公开(公告)号：US20070174555A1
公开(公告)日：2007-07-26
申请号：US11335829
申请日：2006-01-20
申请人： Martin Burtscher , Ilya Ganusov
发明人： Martin Burtscher , Ilya Ganusov
IPC分类号： G06F12/00
CPC分类号： G06F9/3851 , G06F9/30047 , G06F9/3017 , G06F9/3455 , G06F9/3832 , G06F12/0862
摘要： A prefetching technique referred to as future execution (FE) dynamically creates a prefetching thread for each active thread in a processor by simply sending a copy of all committed, register-writing instructions in a primary thread to an otherwise idle processor. On the way to the second processor, a value predictor replaces each predictable instruction with a load immediate instruction, where the immediate is the predicted result that the instruction is likely to produce during its nth next dynamic execution. Executing this modified instruction stream (i.e., the prefetching thread) in another processor allows computation of the future results of the instructions that are not directly predictable. This causes the issuance of prefetches into the shared memory hierarchy, thereby reducing the primary thread's memory access time and speeding up the primary thread's execution.
摘要翻译：称为未来执行（FE）的预取技术通过简单地将主线程中的所有提交的寄存器写入指令的副本发送到另外空闲的处理器来动态地为处理器中的每个活动线程创建预取线程。在到第二处理器的途中，值预测器用负载立即指令替换每个可预测指令，其中立即数是指令在其第n次下一次动态执行期间可能产生的预测结果。在另一个处理器中执行该修改的指令流（即，预取线程）允许计算未直接预测的指令的未来结果。这将导致预取到共享内存层次结构中，从而减少主线程的内存访问时间并加快主线程的执行速度。

7. 发明授权

US08191019B2 Non-predicated to predicated conversion of asynchronous representations 有权
标题翻译：非谓词异步表示的谓词转换
公开(公告)号：US08191019B2
公开(公告)日：2012-05-29
申请号：US12505296
申请日：2009-07-17
申请人： Rajit Manohar , Ilya Ganusov , Virantha Ekanayake , Kamal Chaudhary , Clinton W. Kelly
发明人： Rajit Manohar , Ilya Ganusov , Virantha Ekanayake , Kamal Chaudhary , Clinton W. Kelly
IPC分类号： G06F17/50 , H03K17/00
CPC分类号： G06F17/5045
摘要： Methods, circuits and systems for converting of a non-predicated asynchronous netlist to a predicated asynchronous netlist are described. These may operate to identify one or more portions of an asynchronous netlist corresponding to a partially utilized portion of an asynchronous circuit. The asynchronous netlist may be modified to control the partially utilized portion. Additional methods, circuits, and systems are disclosed.
摘要翻译：描述了用于将非预测异步网表转换为预定异步网表的方法，电路和系统。这些可以操作以识别与异步电路的部分利用部分相对应的异步网表的一个或多个部分。可以修改异步网表以控制部分利用的部分。公开了附加的方法，电路和系统。

8. 发明授权

US07900078B1 Asynchronous conversion circuitry apparatus, systems, and methods 有权
标题翻译：异步转换电路装置，系统和方法
公开(公告)号：US07900078B1
公开(公告)日：2011-03-01
申请号：US12559069
申请日：2009-09-14
申请人： Rajit Manohar , Clinton W. Kelly , Virantha Ekanayake , Christopher LaFrieda , Hong Tam , Ilya Ganusov , Raymond Nijssen , Marcel Van der Goot
发明人： Rajit Manohar , Clinton W. Kelly , Virantha Ekanayake , Christopher LaFrieda , Hong Tam , Ilya Ganusov , Raymond Nijssen , Marcel Van der Goot
IPC分类号： G06F1/04 , H03K19/00 , H04L7/00
CPC分类号： G06F1/12
摘要： Apparatus, systems, and methods operate to receive a sufficient number of asynchronous input tokens at the inputs of an asynchronous apparatus to conduct a specified processing operation, some of the tokens decoded to determine an operation type associated with the specified processing operation; to receive an indication that outputs of the asynchronous apparatus are ready to conduct the specified processing operation; to signal a synchronous circuit to process data included in the tokens according to the specified processing operation; and to convert synchronous outputs from the synchronous circuit into asynchronous output tokens to be provided to outputs of the asynchronous apparatus when the synchronous outputs result from the specified processing operation. Additional apparatus, systems, and methods are disclosed.
摘要翻译：装置，系统和方法操作以在异步装置的输入处接收足够数量的异步输入令牌以进行指定的处理操作，解码的一些令牌以确定与指定的处理操作相关联的操作类型; 以接收异步装置的输出准备好进行指定的处理操作的指示; 根据指定的处理操作，向同步电路发信号处理令牌中包含的数据; 并且当从指定的处理操作产生同步输出时，将来自同步电路的同步输出转换为异步输出令牌，以提供给异步装置的输出。公开了附加装置，系统和方法。

9. 发明申请

US20110012666A1 NON-PREDICATED TO PREDICATED CONVERSION OF ASYNCHRONOUS REPRESENTATIONS 有权
标题翻译：不预测的异常代表的转换
公开(公告)号：US20110012666A1
公开(公告)日：2011-01-20
申请号：US12505296
申请日：2009-07-17
申请人： Rajit Manohar , Ilya Ganusov , Virantha Ekanayake , Kamal Chaudhary , Clinton W. Kelly
发明人： Rajit Manohar , Ilya Ganusov , Virantha Ekanayake , Kamal Chaudhary , Clinton W. Kelly
IPC分类号： H03K17/00 , G06F17/50
CPC分类号： G06F17/5045
摘要： Methods, circuits and systems for converting of a non-predicated asynchronous netlist to a predicated asynchronous netlist are described. These may operate to identify one or more portions of an asynchronous netlist corresponding to a partially utilized portion of an asynchronous circuit. The asynchronous netlist may be modified to control the partially utilized portion. Additional methods, circuits, and systems are disclosed.
摘要翻译：描述了用于将非预测异步网表转换为预定异步网表的方法，电路和系统。这些可以操作以识别与异步电路的部分利用部分相对应的异步网表的一个或多个部分。可以修改异步网表以控制部分利用的部分。公开了附加的方法，电路和系统。

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