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1. 发明授权

US07679414B1 Method and apparatus for tuning delay 有权
标题翻译：调谐延迟的方法和装置
公开(公告)号：US07679414B1
公开(公告)日：2010-03-16
申请号：US12170900
申请日：2008-07-10
申请人： Reuven Ecker , Inbal Gal
发明人： Reuven Ecker , Inbal Gal
IPC分类号： H03H11/06
CPC分类号： H03H11/265 , H03K3/3565 , H03K5/133 , H03K2005/00065 , H03K2005/00071
摘要： Aspects of the disclosure provide a fine tunable digital delay circuit that can be applied in a high frequency digital circuit. Further, the digital delay circuit can utilize a level restoring technique to enable a wide tunable delay range. The delay circuit can include a delay element configured to receive an input signal at an input node and output a controlled signal having a controlled rise time and a controlled fall time at a controlled node, a first plurality of transistors configured to bias a supply node of the delay element to govern the controlled rise time of the controlled signal, and a second plurality of transistors configured to bias a ground node of the delay element to govern the controlled fall time of the controlled signal. The delay circuit can further include a restoring circuit configured to charge or discharge the controlled node.
摘要翻译：本公开的方面提供了可应用于高频数字电路的精细可调数字延迟电路。此外，数字延迟电路可以利用电平恢复技术来实现宽可调延迟范围。延迟电路可以包括延迟元件，其被配置为在输入节点处接收输入信号，并且输出受控信号，受控信号具有被控制的上升时间和受控节点处的受控下降时间;第一多个晶体管，被配置为偏置供电节点所述延迟元件用于控制所述受控信号的受控上升时间;以及第二多个晶体管，被配置为偏置所述延迟元件的接地节点以控制受控信号的受控下降时间。延迟电路还可以包括被配置为对受控节点进行充电或放电的恢复电路。

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