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1. 发明申请

US20150138862A1 THREE-DIMENSIONAL SEMICONDUCTOR DEVICES AND FABRICATING METHODS THEREOF 有权
标题翻译：三维半导体器件及其制作方法
公开(公告)号：US20150138862A1
公开(公告)日：2015-05-21
申请号：US14523977
申请日：2014-10-27
申请人： JINTAEK PARK , YOUNGWOO PARK , JAEDUK LEE
发明人： JINTAEK PARK , YOUNGWOO PARK , JAEDUK LEE
IPC分类号： G11C16/04 , G11C16/10 , H01L27/115 , H01L27/092 , H01L29/792
CPC分类号： H01L27/11573 , G11C5/02 , G11C5/025 , G11C16/0466 , G11C16/0483 , G11C16/10 , H01L27/0688 , H01L27/092 , H01L27/1157 , H01L27/11575 , H01L27/11582
摘要： A three-dimensional (3D) semiconductor memory device includes a CMOS circuit structure including a plurality of column blocks each comprising a plurality of page buffer circuits, and a lower wiring structure and a memory structure sequentially stacked over the CMOS circuit structure. The memory structure overlaps a first circuit region of the CMOS circuit structure and does not overlap a second circuit region of the CMOS circuit structure, and the plurality of column blocks are contained within the first circuit region of the CMOS circuit structure.
摘要翻译：三维（3D）半导体存储器件包括CMOS电路结构，其包括多个列块，每个列块包括多个页缓冲器电路，以及顺序堆叠在CMOS电路结构上的下布线结构和存储器结构。存储器结构与CMOS电路结构的第一电路区域重叠，并且不与CMOS电路结构的第二电路区域重叠，并且多个列块被包含在CMOS电路结构的第一电路区域内。

2. 发明申请

US20110169068A1 NON-VOLATILE MEMORY DEVICES HAVING A FLOATING GATE CAP BETWEEN A FLOATING GATE AND A GATE INSULATING LAYER 有权
标题翻译：具有浮动门和门绝缘层之间的浮动门盖的非易失性存储器件
公开(公告)号：US20110169068A1
公开(公告)日：2011-07-14
申请号：US12986553
申请日：2011-01-07
申请人： JAEDUK LEE , Albert Fayrushin , ByungKyu Cho , Jungdal Choi , Sunghoi Hur , Kwang Soo Seol , Dohyun Lee
发明人： JAEDUK LEE , Albert Fayrushin , ByungKyu Cho , Jungdal Choi , Sunghoi Hur , Kwang Soo Seol , Dohyun Lee
IPC分类号： H01L29/788
CPC分类号： H01L29/42336 , H01L27/11521 , H01L29/42324 , H01L29/4234 , H01L29/42352 , H01L29/7881 , H01L29/792
摘要： Provided are nonvolatile memory devices and a method of forming the same. A tunnel insulating pattern is provided on a substrate, and a floating gate is provided on the tunnel insulating pattern. A floating gate cap having a charge trap site is provided on the floating gate, and a gate dielectric pattern is provided on the floating gate cap. A control gate is provided on the gate dielectric pattern.
摘要翻译：提供了非易失性存储器件及其形成方法。隧道绝缘图案设置在基板上，并且浮动栅极设置在隧道绝缘图案上。在浮置栅极上设置具有电荷陷阱位置的浮动栅极盖，并且在浮动栅极盖上设置栅极电介质图案。控制栅极设置在栅极电介质图案上。

3. 发明授权

US09362303B2 Semiconductor memory devices including fine patterns and methods of fabricating the same 有权
标题翻译：包括精细图案的半导体存储器件及其制造方法
公开(公告)号：US09362303B2
公开(公告)日：2016-06-07
申请号：US14681505
申请日：2015-04-08
申请人： Jaegoo Lee , Youngwoo Park , Jaeduk Lee
发明人： Jaegoo Lee , Youngwoo Park , Jaeduk Lee
IPC分类号： H01L29/792 , H01L27/115 , H01L29/66 , H01L21/28 , H01L21/768 , H01L21/285
CPC分类号： H01L27/11582 , H01L21/28282 , H01L21/28518 , H01L21/76877 , H01L29/66833 , H01L29/7926
摘要： Semiconductor devices are provided including an active pillar protruding from a substrate; a first gate electrode and a second gate electrode adjacent to a sidewall of the active pillar and vertically overlapping with each other, the first and second gate electrodes being insulated from each other; a first intergate insulating layer covering a first surface of the first gate electrode; and a second intergate insulating layer covering a second surface, opposite the first surface, of the second gate electrode and spaced apart from the first intergate insulating layer. The first intergate insulating layer and the second intergate insulating layer define an air gap therebetween.
摘要翻译：提供半导体器件，其包括从基板突出的有源柱; 与所述有源柱的侧壁相邻并且彼此垂直重叠的第一栅电极和第二栅电极，所述第一栅电极和所述第二栅电极彼此绝缘; 覆盖所述第一栅电极的第一表面的第一隔间绝缘层; 以及覆盖所述第二栅电极的与所述第一表面相对的第二表面并与所述第一栅极绝缘层间隔开的第二栅极绝缘层。第一隔间绝缘层和第二隔间绝缘层在其间形成气隙。

4. 发明授权

US09183893B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09183893B2
公开(公告)日：2015-11-10
申请号：US14037547
申请日：2013-09-26
申请人： Kohji Kanamori , Youngwoo Park , Jintaek Park , Kwang Soo Seol , Jaeduk Lee
发明人： Kohji Kanamori , Youngwoo Park , Jintaek Park , Kwang Soo Seol , Jaeduk Lee
IPC分类号： G11C5/06 , G11C13/00 , H01L45/00 , H01L27/22 , H01L27/24
CPC分类号： G11C5/06 , G11C5/063 , G11C13/0002 , G11C13/0023 , G11C2213/73 , H01L27/222 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147
摘要： According to example embodiments of inventive concepts, a semiconductor memory devices includes: a plurality of memory blocks that each include a plurality of stack structures, global bit lines connected in common to the plurality of memory blocks, block selection lines configured to control electrical connect between the global bit lines and one of the plurality of memory blocks, and vertical selection lines configured to control electrical connected between the global bit lines and one of the plurality of stack structures. Each of the plurality of stack structures includes a plurality of local bit lines, first vertical word lines and second vertical word lines crossing first sidewalls and second sidewalls respectfully of the plurality of stack structures, first variable resistive elements between the plurality of stack structures and the first vertical word lines, and second variable resistive elements between the plurality of stack structures and the second vertical word lines.
摘要翻译：根据本发明构思的示例性实施例，半导体存储器件包括：多个存储器块，每个存储块包括多个堆叠结构，共同连接到多个存储器块的全局位线，被配置为控制全局位线和多个存储器块中的一个以及垂直选择线，其被配置为控制连接在全局位线和多个堆叠结构中的一个之间的电连接。多个堆叠结构中的每一个包括多个局部位线，第一垂直字线和第二垂直字线，其横向于多个堆叠结构的第一侧壁和第二侧壁相交，多个堆叠结构之间的第一可变电阻元件和第一垂直字线和第二可变电阻元件在多个堆叠结构和第二垂直字线之间。

5. 发明申请

US20140306279A1 SEMICONDUCTOR DEVICES INCLUDING WORD LINE INTERCONNECTING STRUCTURES 有权
标题翻译：包括字线互连结构的半导体器件
公开(公告)号：US20140306279A1
公开(公告)日：2014-10-16
申请号：US14191542
申请日：2014-02-27
申请人： Jintaek Park , Youngwoo Park , Jaeduk Lee
发明人： Jintaek Park , Youngwoo Park , Jaeduk Lee
IPC分类号： H01L23/00 , H01L27/115
CPC分类号： H01L27/11556 , H01L27/11582 , H01L29/7889 , H01L29/7926
摘要： A semiconductor memory device includes a substrate including a cell region and an interconnection region, adjacent first and second rows of vertical channels extending vertically from the substrate in the cell region, and layers of word lines stacked on the substrate. Each layer includes a first word line through which the first row of vertical channels passes and a second word line through which the second row of vertical channels passes, and the word lines include respective word line pads extending into the interconnection region. An isolation pattern separates the first and second word lines in the cell region and the interconnection region. First and second pluralities of contact plugs are disposed on opposite sides of the isolation pattern in the interconnection region and contact the word line pads.
摘要翻译：半导体存储器件包括：衬底，其包括单元区域和互连区域;相邻的从单元区域中的衬底垂直延伸的第一和第二排垂直沟道以及堆叠在衬底上的字线层。每层包括第一行垂直通道通过的第一字线和第二行垂直通道通过的第二字线，并且字线包括延伸到互连区域中的相应字线焊盘。隔离图案分离单元区域和互连区域中的第一和第二字线。第一和第二多个接触插塞设置在互连区域中的隔离图案的相对侧上，并与字线焊盘接触。

6. 发明申请

US20180122695A1 SEMICONDUCTOR DEVICE HAVING INTERCONNECTION STRUCTURE 有权
公开(公告)号：US20180122695A1
公开(公告)日：2018-05-03
申请号：US15857961
申请日：2017-12-29
申请人： Dohyun LEE , Youngwoo PARK , Junghoon PARK , Jaeduk LEE
发明人： Dohyun LEE , Youngwoo PARK , Junghoon PARK , Jaeduk LEE
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L21/76877 , H01L21/76816 , H01L23/522 , H01L23/5226 , H01L23/5283 , H01L23/53266 , H01L23/53295 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： A semiconductor device includes a semiconductor pattern on a semiconductor substrate, a three-dimensional memory array on the semiconductor pattern, and a peripheral interconnection structure between the semiconductor pattern and the semiconductor substrate. The peripheral interconnection structure includes an upper interconnection structure on a lower interconnection structure. The upper interconnection structure includes an upper interconnection and an upper barrier layer. The lower interconnection structure includes a lower interconnection and a lower barrier layer. The upper barrier layer is under a bottom surface of the upper interconnection and does not cover side surfaces of the upper interconnection. The lower barrier layer is under a bottom surface of the lower interconnection and covers side surfaces of the lower interconnection.

7. 发明授权

US09601204B2 Three-dimensional semiconductor devices and fabricating methods thereof 有权
公开(公告)号：US09601204B2
公开(公告)日：2017-03-21
申请号：US14523977
申请日：2014-10-27
申请人： Jintaek Park , Youngwoo Park , Jaeduk Lee
发明人： Jintaek Park , Youngwoo Park , Jaeduk Lee
IPC分类号： G11C5/02 , G11C16/04 , G11C16/10 , H01L27/115 , H01L27/06 , H01L27/092
CPC分类号： H01L27/11573 , G11C5/02 , G11C5/025 , G11C16/0466 , G11C16/0483 , G11C16/10 , H01L27/0688 , H01L27/092 , H01L27/1157 , H01L27/11575 , H01L27/11582
摘要： A three-dimensional (3D) semiconductor memory device includes a CMOS circuit structure including a plurality of column blocks each comprising a plurality of page buffer circuits, and a lower wiring structure and a memory structure sequentially stacked over the CMOS circuit structure. The memory structure overlaps a first circuit region of the CMOS circuit structure and does not overlap a second circuit region of the CMOS circuit structure, and the plurality of column blocks are contained within the first circuit region of the CMOS circuit structure.

8. 发明申请

US20170047343A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：三维半导体存储器件
公开(公告)号：US20170047343A1
公开(公告)日：2017-02-16
申请号：US15208669
申请日：2016-07-13
申请人： Dohyun LEE , Younghwan SON , Minyeong SONG , YOUNGWOO PARK , Jaeduk LEE
发明人： Dohyun LEE , Younghwan SON , Minyeong SONG , YOUNGWOO PARK , Jaeduk LEE
IPC分类号： H01L27/115 , G11C16/08 , G11C16/26 , H01L29/167 , G11C16/10
CPC分类号： H01L27/11582 , H01L27/11529 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L29/167
摘要： Provided is a three-dimensional semiconductor memory device including a peripheral logic structure on a semiconductor substrate to include peripheral logic circuits and a lower insulating gapfill layer, a horizontal semiconductor layer on the peripheral logic structure, stacks on the horizontal semiconductor layer, each of the stacks including a plurality of electrodes vertically stacked on the horizontal semiconductor layer, and a plurality of vertical structures passing through the stacks and connected to the horizontal semiconductor layer. The horizontal semiconductor layer may include a first semiconductor layer disposed on the lower insulating gapfill layer and co-doped with an anti-diffusion material and first conductivity type impurities of a first impurity concentration, and a second semiconductor layer disposed on the first semiconductor layer and doped with first conductivity type impurities of a second impurity concentration lower than the first impurity concentration or undoped.
摘要翻译：提供一种三维半导体存储器件，其包括在半导体衬底上的外围逻辑结构，包括外围逻辑电路和下部绝缘间隙填充层，外围逻辑结构上的水平半导体层，堆叠在水平半导体层上，包括垂直堆叠在水平半导体层上的多个电极的堆叠和穿过堆叠并连接到水平半导体层的多个垂直结构。水平半导体层可以包括设置在下绝缘间隙填充层上并与反扩散材料共掺杂的第一半导体层和第一杂质浓度的第一导电型杂质，以及设置在第一半导体层上的第二半导体层，掺杂具有低于第一杂质浓度的第二杂质浓度的第一导电型杂质或未掺杂的。

9. 发明申请

US20170040338A1 SEMICONDUCTOR MEMORY DEVICES HAVING CLOSELY SPACED BIT LINES 审中-公开
标题翻译：具有密闭空间位线的半导体存储器件
公开(公告)号：US20170040338A1
公开(公告)日：2017-02-09
申请号：US14989955
申请日：2016-01-07
申请人： Jaeduk LEE , Youngwoo PARK
发明人： Jaeduk LEE , Youngwoo PARK
IPC分类号： H01L27/115 , H01L23/528
CPC分类号： H01L27/11582 , H01L27/0688 , H01L27/11573
摘要： The inventive concepts relate to a semiconductor memory device. The semiconductor memory device includes a substrate including a circuit region and first and second connection regions respectively disposed at both sides of the circuit region opposite to each other, a logic structure including a logic circuit disposed on the circuit region and a lower insulating layer covering the logic circuit, and a memory structure on the logic structure. The logic circuit includes a first page buffer disposed adjacently to the first connection region and a second page buffer disposed adjacently to the second connection region. The memory structure includes bit lines extending onto at least one of the first and second connection regions.
摘要翻译：本发明构思涉及半导体存储器件。半导体存储器件包括：基板，包括电路区域和分别设置在彼此相反的电路区域的两侧的第一和第二连接区域;逻辑结构，包括布置在电路区域上的逻辑电路和覆盖逻辑电路和逻辑结构上的存储器结构。逻辑电路包括与第一连接区域相邻设置的第一页缓冲器和与第二连接区域相邻设置的第二页缓冲器。存储器结构包括延伸到第一和第二连接区域中的至少一个的位线。

10. 发明申请

US20160118399A1 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：三维半导体存储器件
公开(公告)号：US20160118399A1
公开(公告)日：2016-04-28
申请号：US14878453
申请日：2015-10-08
申请人： YUNGHWAN SON , JAESUNG SIM , SHINHWAN KANG , YOUNGWOO PARK , JAEDUK LEE
发明人： YUNGHWAN SON , JAESUNG SIM , SHINHWAN KANG , YOUNGWOO PARK , JAEDUK LEE
IPC分类号： H01L27/115 , H01L29/34 , G11C16/30
CPC分类号： H01L27/11575 , G11C5/025 , G11C16/0483 , G11C16/30 , H01L27/11517 , H01L27/11526 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11582 , H01L29/34
摘要： A three-dimensional (3D) semiconductor memory device that includes a peripheral logic structure including peripheral logic circuits disposed on a semiconductor substrate and a first insulation layer overlapping the peripheral logic circuits, and a plurality of memory blocks spaced apart from each other on the peripheral logic structure.At least one of the memory blocks includes a well plate electrode, a semiconductor layer in contact with a first surface of the well plate electrode, a stack structure including a plurality of electrodes vertically stacked on the semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to the semiconductor layer.
摘要翻译：一种三维（3D）半导体存储器件，其包括外围逻辑结构，该外围逻辑结构包括设置在半导体衬底上的外围逻辑电路和与外围逻辑电路重叠的第一绝缘层，以及在周边彼此间隔开的多个存储块逻辑结构。存储块中的至少一个包括阱板电极，与阱板电极的第一表面接触的半导体层，包括垂直堆叠在半导体层上的多个电极的堆叠结构，以及多个垂直结构穿透堆叠结构并连接到半导体层。

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