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1. 发明授权

US08117577B1 Determining timing paths within a circuit block of a programmable integrated circuit 有权
标题翻译：确定可编程集成电路的电路块内的定时路径
公开(公告)号：US08117577B1
公开(公告)日：2012-02-14
申请号：US12361516
申请日：2009-01-28
申请人： Vasisht M. Vadi , Alvin Y. Ching , Subodh Kumar , Richard D. Freeman , Ian L. McEwen , Philip R. Haratsaris , Jaime D. Lujan , Eric M. Schwarz
发明人： Vasisht M. Vadi , Alvin Y. Ching , Subodh Kumar , Richard D. Freeman , Ian L. McEwen , Philip R. Haratsaris , Jaime D. Lujan , Eric M. Schwarz
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5054 , G06F17/5031 , G06F2217/84
摘要： A computer-implemented method of identifying timing paths of a circuit block can include representing a circuit block including at least one bypassable component as a block diagram having a plurality of elements linked by nodes. The method can include generating a map file including a text description of each element within the block diagram, wherein the text description of each element specifies a bypass indicator for the element. The method also can include generating a plurality of sub-paths from the map file, determining timing paths from the plurality of sub-paths by selectively combining different ones of the plurality of sub-paths according to commonality of starting points and ending points of the plurality of sub-paths, and outputting the timing paths.
摘要翻译：识别电路块的定时路径的计算机实现的方法可以包括表示包括至少一个可旁路组件的电路块作为具有由节点链接的多个元件的框图。该方法可以包括生成包括框图中每个元素的文本描述的地图文件，其中每个元素的文本描述指定该元素的旁路指示符。该方法还可以包括从地图文件生成多个子路径，根据多个子路径的起始点和终点的共同点选择性地组合多个子路径中的不同子路径，从多个子路径确定定时路径多个子路径，并输出定时路径。

2. 发明授权

US07840925B1 Source specific timing checks on synchronous elements using a static timing analysis engine 有权
标题翻译：使用静态时序分析引擎对同步元素进行源特定定时检查
公开(公告)号：US07840925B1
公开(公告)日：2010-11-23
申请号：US12047502
申请日：2008-03-13
申请人： Jaime D. Lujan , Mario Escobar
发明人： Jaime D. Lujan , Mario Escobar
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A computer-implemented method of performing timing analysis upon a circuit design having synchronous circuit elements can include selecting a destination pin having a plurality of source pins, wherein each source pin of the plurality of source pins defines a data path to the destination pin. A slack of a selected path of the data paths to the destination pin can be determined. A timing adjustment of each of the plurality of source pins can be compared to the slack of the selected path, wherein each timing adjustment is determined using static timing analysis. A simulation node can be selectively included within the circuit design according to the comparison. The circuit design can be output.
摘要翻译：在具有同步电路元件的电路设计上执行定时分析的计算机实现的方法可以包括选择具有多个源极引脚的目的地引脚，其中多个源极引脚中的每个源极引脚定义到目标引脚的数据路径。可以确定到目的地引脚的数据路径的选定路径的松弛。可以将多个源极引脚中的每一个的定时调整与所选择的路径的松弛进行比较，其中使用静态时序分析来确定每个定时调整。根据比较可以在电路设计中选择性地包括模拟节点。可以输出电路设计。

3. 发明授权

US07810055B1 Design independent correlation data storage for use with physical design of programmable logic devices 有权
标题翻译：设计独立的相关数据存储，用于可编程逻辑器件的物理设计
公开(公告)号：US07810055B1
公开(公告)日：2010-10-05
申请号：US11633962
申请日：2006-12-05
申请人： Brian J. Alexander , Jaime D. Lujan , W. Story Leavesley, III
发明人： Brian J. Alexander , Jaime D. Lujan , W. Story Leavesley, III
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method of managing correlation data for a design implementation process can include identifying correlation data from each of a plurality of design applications. Each of the design applications can generate a circuit description and the correlation data can specify associations between circuit elements of different ones of the circuit descriptions. The method also can include storing the circuit descriptions and the correlation data independently of one another and determining a relationship among circuit elements of the circuit descriptions according to the correlation data.
摘要翻译：管理设计实现过程的相关数据的方法可以包括从多个设计应用中的每一个识别相关数据。每个设计应用可以产生电路描述，并且相关数据可以指定不同电路描述的电路元件之间的关联。该方法还可以包括彼此独立地存储电路描述和相关数据，并根据相关数据确定电路描述的电路元件之间的关系。

4. 发明授权

US07451417B1 Timing annotation accuracy through the use of static timing analysis tools 有权
标题翻译：定时注释精度通过使用静态时序分析工具
公开(公告)号：US07451417B1
公开(公告)日：2008-11-11
申请号：US11433127
申请日：2006-05-12
申请人： Scott J. Campbell , Mario Escobar , Jaime D. Lujan , Walter A. Manaker, Jr. , Brian D. Philofsky
发明人： Scott J. Campbell , Mario Escobar , Jaime D. Lujan , Walter A. Manaker, Jr. , Brian D. Philofsky
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A method of generating timing information for a circuit design can include determining static timing data for the circuit design and identifying a source of timing information for use in functional simulation of the circuit design. The method also can include updating the source of timing information to include at least a portion of the static timing data.
摘要翻译：一种产生电路设计的定时信息的方法可以包括确定用于电路设计的静态定时数据，并且识别在电路设计的功能仿真中使用的定时信息源。该方法还可以包括更新定时信息源以包括静态定时数据的至少一部分。

5. 发明授权

US07421675B1 Annotating timing information for a circuit design for increased timing accuracy 有权
标题翻译：注释电路设计的时序信息，提高定时精度
公开(公告)号：US07421675B1
公开(公告)日：2008-09-02
申请号：US11333863
申请日：2006-01-17
申请人： Scott J. Campbell , Mario Escobar , Jaime D. Lujan , Walter A. Manaker, Jr. , Brian D. Philofsky
发明人： Scott J. Campbell , Mario Escobar , Jaime D. Lujan , Walter A. Manaker, Jr. , Brian D. Philofsky
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5031
摘要： A method of annotating timing information for a circuit design for performing timing analysis can include determining minimum and maximum clock path delays for registers of a circuit design and computing a difference between the maximum clock path delay and the minimum clock path delay for a destination register of the circuit design. The method further can include adjusting a register timing parameter for the destination register according to the difference and performing a timing verification on the destination register using the adjusted register timing parameter.
摘要翻译：注意用于执行定时分析的电路设计的定时信息的方法可以包括确定用于电路设计的寄存器的最小和最大时钟路径延迟，以及计算目的寄存器的目的地寄存器的最大时钟路径延迟和最小时钟路径延迟之间的差异电路设计。该方法还可以包括根据差值调整目的地寄存器的寄存器定时参数，并使用经调整的寄存器定时参数在目的地寄存器上执行定时验证。

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