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1. 发明授权

US08372743B2 Hybrid pitch-split pattern-split lithography process 有权
标题翻译：混合音调分割图案分割光刻工艺
公开(公告)号：US08372743B2
公开(公告)日：2013-02-12
申请号：US13410145
申请日：2012-03-01
申请人： James Walter Blatchford
发明人： James Walter Blatchford
IPC分类号： H01L21/4763
CPC分类号： H01L21/76816 , G03F7/70466 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit may be formed by a process of forming a three interconnect patterns in a plurality of parallel route tracks, using photolithography processes which have illumination sources capable of a pitch distance twice the pitch distance of the parallel route tracks. The first interconnect pattern includes a first lead pattern which extends to a first point. The second interconnect pattern includes a second lead pattern which is parallel to and immediately adjacent to the first lead pattern. The third interconnect pattern includes a third lead pattern which is parallel to and immediately adjacent to the second pattern and which extends to a second point in the first instance of the parallel route tracks, laterally separated from the first point by a distance less than one and one-half times a space between adjacent patterns in the parallel route tracks.
摘要翻译：可以通过使用具有能够将间距距离为平行路径轨道的间距距离的两倍的照明源的光刻处理，通过在多个平行路径轨道中形成三个互连图案的处理来形成集成电路。第一互连图案包括延伸到第一点的第一引线图案。第二布线图案包括与第一引线图案平行并且紧邻第一引线图案的第二引线图案。第三互连图案包括与第二图案平行并且紧邻第二图案的第三引线图案，并且延伸到第一平行路径轨道中的第二点，与第一点横向分开一小于一个的距离，在平行路径轨迹中的相邻图案之间的空间的一半。

2. 发明授权

US08304317B2 Gate line edge roughness reduction by using 2P/2E process together with high temperature bake 有权
标题翻译：通过使用2P / 2E工艺与高温烘烤进行栅极边缘粗糙度降低
公开(公告)号：US08304317B2
公开(公告)日：2012-11-06
申请号：US12648802
申请日：2009-12-29
申请人： Yiming Gu , James Walter Blatchford
发明人： Yiming Gu , James Walter Blatchford
IPC分类号： H01L21/8324
CPC分类号： H01L21/28123 , H01L21/32139
摘要： A method of patterning a plurality of polysilicon structures includes forming a polysilicon layer over a semiconductor body, and patterning the polysilicon layer to form a first polysilicon structure using a first patterning process that reduces line-edge roughness (LER). The method further includes patterning the polysilicon layer to form a second polysilicon structure using a second patterning process that is different from the first patterning process after performing the first patterning process.
摘要翻译：图案化多个多晶硅结构的方法包括在半导体本体上形成多晶硅层，并使用减少线边缘粗糙度（LER）的第一图案化工艺来图案化多晶硅层以形成第一多晶硅结构。该方法还包括使用在执行第一图案化工艺之后与第一图案化工艺不同的第二图案化工艺来图案化多晶硅层以形成第二多晶硅结构。

3. 发明申请

US20120235242A1 Control of Local Environment for Polysilicon Conductors in Integrated Circuits 有权
标题翻译：集成电路中多晶硅导体的局部环境控制
公开(公告)号：US20120235242A1
公开(公告)日：2012-09-20
申请号：US13049862
申请日：2011-03-16
申请人： James Walter Blatchford, JR. , Yong Seok Choi
发明人： James Walter Blatchford, JR. , Yong Seok Choi
IPC分类号： H01L27/04 , H01L21/336
CPC分类号： H01L29/66484 , H01L21/28123 , H01L21/823828 , H01L27/0207 , H01L29/78
摘要： A method of fabricating gate level electrodes and interconnects in an integrated circuit, and an integrated circuit so fabricated, with improved process margin for the gate level interconnects of a width near the critical dimension. Off-axis illumination, as used in the photolithography of deep sub-micron critical dimension, is facilitated by the patterned features having a preferred orientation in a common direction, with a pitch constrained to within a relatively narrow range. Interconnects in that same gate level, for example “field poly” interconnects, that run parallel to an array of gate elements are placed within a specified distance range from the ends of the gate elements, or at a distance sufficient to allow sub-resolution assist features.
摘要翻译：一种在集成电路中制造栅极电极和互连的方法，以及如此制造的集成电路，其具有改进的临界尺寸附近的栅极级互连的工艺裕度。在深亚微米临界尺寸的光刻中使用的离轴照明通过具有在相同方向上具有优选取向的图案化特征促进，其间距限制在相对较窄的范围内。在与栅极元件阵列平行的同一栅极级别（例如，“多晶”互连）的互连被放置在从栅极元件的端部指定的距离范围内，或者距离足以允许次级分辨率辅助特征。

4. 发明申请

US20120225551A1 PATTERN-SPLIT DECOMPOSITION STRATEGY FOR DOUBLE-PATTERNED LITHOGRAPHY PROCESS 有权
标题翻译：用于双模式平移过程的分形分解策略
公开(公告)号：US20120225551A1
公开(公告)日：2012-09-06
申请号：US13410188
申请日：2012-03-01
申请人： James Walter Blatchford
发明人： James Walter Blatchford
IPC分类号： H01L21/768
CPC分类号： H01L21/76816 , G03F7/70466 , H01L21/0274 , H01L21/31144 , H01L21/76838 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit may be formed by a process of forming a first interconnect pattern in a plurality of parallel route tracks, and forming a second interconnect pattern in the plurality of parallel route tracks. The first interconnect pattern includes a first lead pattern which extends to a first point in an instance of the first plurality of parallel route tracks, and the second interconnect pattern includes a second lead pattern which extends to a second point in the same instance of the plurality of parallel route tracks, such that the second point is laterally separated from the first point by a distance one to one and one-half times a space between adjacent parallel lead patterns in the plurality of parallel route tracks. A metal interconnect formation process is performed which forms metal interconnect lines in an interconnect level defined by the first interconnect pattern and the second interconnect pattern.
摘要翻译：可以通过在多个平行路径轨道中形成第一互连图案并在多个平行路径轨道中形成第二互连图案的过程来形成集成电路。第一互连图案包括在第一多个平行路径轨道的情况下延伸到第一点的第一引线图案，并且第二互连图案包括延伸到多个平行路径的相同实例中的第二点的第二引线图案平行路径轨道，使得第二点与第一点横向分离距离在多个平行路线轨道中的相邻平行引线图案之间的空间的一至二分之一的距离。执行金属互连形成工艺，其形成由第一互连图案和第二互连图案限定的互连层中的金属互连线。

5. 发明授权

US07910289B2 Use of dual mask processing of different composition such as inorganic/organic to enable a single poly etch using a two-print-two-etch approach 有权
标题翻译：使用不同成分的双掩模加工，如无机/有机，可使用双印双蚀刻方法进行单层聚蚀刻
公开(公告)号：US07910289B2
公开(公告)日：2011-03-22
申请号：US11326392
申请日：2006-01-06
申请人： Benjamen Michael Rathsack , James Walter Blatchford , Steven Arthur Vitale
发明人： Benjamen Michael Rathsack , James Walter Blatchford , Steven Arthur Vitale
IPC分类号： G03F7/20
CPC分类号： H01L21/027 , H01L21/033 , H01L21/32139
摘要： In accordance with the invention, there are methods of making an integrated circuit, an integrated circuit device, and a computer readable medium. A method can comprise forming a first layer over a semiconductor substrate, forming a first mask layer over the semiconductor substrate, and using the first mask layer to pattern first features. The method can also include forming a second mask layer over the first features, using the second mask layer to pattern portions of the first features, removing the second mask layer, and removing the first mask layer.
摘要翻译：根据本发明，存在制造集成电路，集成电路器件和计算机可读介质的方法。一种方法可以包括在半导体衬底上形成第一层，在半导体衬底上形成第一掩模层，以及使用第一掩模层来图案化第一特征。该方法还可以包括在第一特征上形成第二掩模层，使用第二掩模层来图案化第一特征的部分，去除第二掩模层，以及去除第一掩模层。

6. 发明授权

US07737016B2 Two-print two-etch method for enhancement of CD control using ghost poly 有权
标题翻译：双印刷双蚀刻方法，用于增强使用ghost poly的CD控制
公开(公告)号：US07737016B2
公开(公告)日：2010-06-15
申请号：US11482041
申请日：2006-07-07
申请人： James Walter Blatchford , Benjamen Michael Rathsack
发明人： James Walter Blatchford , Benjamen Michael Rathsack
IPC分类号： H01L21/3205
CPC分类号： H01L21/32139 , G03F1/30 , G03F1/70 , G03F7/0035
摘要： According to various embodiments, two-print two-etch methods and devices are disclosed that can be used to form features, such as ghost features, on a substrate. The disclosed methods can be incorporated into, for example, altPSM, attPSM, and binary lithographic method for making semiconductor devices. a method of forming a semiconductor device is provided. The exemplary methods can include defining a plurality of first features and at least one ghost feature on a photosensitive layer by exposing a first mask to a light, wherein the first mask comprises a plurality of phase shift areas that change a phase of the light. A portion of a layer disposed under the photosensitive layer can be removed by etching to form the plurality of first features and the at least one ghost feature. One or more structures not requiring phase shifting can then be defined on the photosensitive layer by exposing a second mask to the light, wherein the second mask removes the at least one ghost feature. A second portion of the layer disposed under the photosensitive layer can then be removed by etching to form one or more structures not requiring phase shifting, wherein the second portion includes the at least one ghost feature.
摘要翻译：根据各种实施例，公开了可以用于在基板上形成诸如重影特征的特征的双印刷双蚀刻方法和装置。所公开的方法可以结合到例如altPSM，attPSM和用于制造半导体器件的二元光刻方法中。提供了形成半导体器件的方法。示例性方法可以包括通过将第一掩模曝光于光而在感光层上限定多个第一特征和至少一个重影特征，其中第一掩模包括改变光的相位的多个相移区域。设置在感光层下方的层的一部分可以通过蚀刻去除以形成多个第一特征和至少一个重影特征。然后可以通过将第二掩模暴露于光而在感光层上限定不需要相移的一个或多个结构，其中第二掩模移除至少一个重影特征。然后可以通过蚀刻去除设置在感光层下方的层的第二部分，以形成不需要相移的一个或多个结构，其中第二部分包括至少一个重影特征。

7. 发明申请

US20090300567A1 DESIGN LAYOUT OF PRINTABLE ASSIST FEATURES TO AID TRANSISTOR CONTROL 有权
标题翻译：可设计的辅助功能设计布局，用于辅助晶体管控制
公开(公告)号：US20090300567A1
公开(公告)日：2009-12-03
申请号：US12131370
申请日：2008-06-02
申请人： Benjamen Michael Rathsack , James Walter Blatchford
发明人： Benjamen Michael Rathsack , James Walter Blatchford
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Exemplary embodiments provide a method for laying out an IC design and the IC design layout. The IC design layout can include one or more gate features placed on an active region including a first pitch (p1) between any two adjacent gate features. Additionally, the IC design layout can include a printable-gate-assist feature placed adjacent to at least one side of the active region, and placed parallel to and at a second pitch (p2) from one first gate feature of the one or more gate features. In various embodiments, a printable-gate-extension feature can be drawn in the design to extend a second gate feature to match a length with a longer neighboring gate feature of the one or more gate features.
摘要翻译：示例性实施例提供了一种用于布置IC设计和IC设计布局的方法。 IC设计布局可以包括放置在有源区域上的一个或多个栅极特征，包括任意两个相邻栅极特征之间的第一间距（p1）。此外，IC设计布局可以包括邻近有源区域的至少一侧放置的可打印门辅助功能，并且平行于并且以一个或多个栅极的一个第一栅极特征的第二间距（p2）放置特征。在各种实施例中，可以在设计中绘制可印刷门延伸特征以扩展第二栅极特征以将长度与一个或多个栅极特征的较长相邻栅极特征相匹配。

8. 发明申请

US20090125865A1 SYSTEM AND METHOD FOR MAKING PHOTOMASKS 有权
标题翻译：制作光子的系统和方法
公开(公告)号：US20090125865A1
公开(公告)日：2009-05-14
申请号：US11940270
申请日：2007-11-14
申请人： Thomas J. Aton , Carl A. Vickery , Frank Scott Johnson , James Walter Blatchford , Benjamen Michael Rathsack , Benjamin McKee
发明人： Thomas J. Aton , Carl A. Vickery , Frank Scott Johnson , James Walter Blatchford , Benjamen Michael Rathsack , Benjamin McKee
IPC分类号： G06F17/50 , H05K1/00
CPC分类号： G03F1/36
摘要： The present disclosure is directed a method for preparing photomask patterns. The method comprises receiving drawn pattern data for a design database. The drawn pattern data describes first device features and second device features, the second device features being associated with design specifications for providing a desired connectivity of the first device features to the second device features. At least a first plurality of the first device features have drawn patterns that will not result in sufficient coverage to effect the desired connectivity. Photomask patterns are formed for the first device features, wherein the photomask patterns for the first plurality of the first device features will result in the desired coverage. Integrated circuit devices formed using the principles of the present disclosure are also taught.
摘要翻译：本公开涉及一种制备光掩模图案的方法。该方法包括接收用于设计数据库的绘制图案数据。所绘制的图案数据描述了第一设备特征和第二设备特征，第二设备特征与用于向第二设备特征提供第一设备特征的期望连接性的设计规范相关联。至少第一多个第一设备特征具有不会导致足够的覆盖以实现期望的连接性的图形。为第一器件特征形成光掩模图案，其中用于第一多个第一器件特征的光掩模图案将导致期望的覆盖。还教导了使用本公开的原理形成的集成电路器件。

9. 发明申请

US20080134128A1 MAXIMUM/VARIABLE SHIFTER WIDTHS TO ALLOW ALTERNATING PHASE-SHIFT IMPLEMENTATION FOR DENSE OR EXISTING LAYOUTS 有权
标题翻译：最大/可变宽度的宽度允许替代相位转换实现渗透或现有的层
公开(公告)号：US20080134128A1
公开(公告)日：2008-06-05
申请号：US11565215
申请日：2006-11-30
申请人： James Walter BLATCHFORD , Carl Albert Vickery
发明人： James Walter BLATCHFORD , Carl Albert Vickery
IPC分类号： G06F17/50
CPC分类号： G03F1/30
摘要： In accordance with an embodiment of the invention, there is a method of designing a lithography mask. The method can comprise determining a maximum width of a shifter, wherein the maximum width corresponds to a width of a shifter for a first set of features and determining whether the shifter having the maximum width can be placed in a shifter space for a second set of features. The method can also comprise incrementally decreasing the width of the shifter to be placed into the shifter space for the second set of features when the shifter having the maximum width cannot be placed in the shifter space for a feature in the second set of features until an acceptable shifter width can be determined or until the shifter width is reduced to a predetermined minimum shifter width.
摘要翻译：根据本发明的实施例，存在设计光刻掩模的方法。该方法可以包括确定移位器的最大宽度，其中最大宽度对应于用于第一组特征的移位器的宽度，并且确定具有最大宽度的移位器是否可以被放置在第二组的移位器空间中特征。当具有最大宽度的移位器不能被放置在用于第二组特征中的特征的移位器空间中时，该方法还可以包括递增地减小要放置到用于第二组特征的移位器空间中的移位器的宽度，可以确定可接受的移位器宽度，或者直到移位器宽度减小到预定的最小移位器宽度。

10. 发明授权

US10741489B2 Rectangular via for ensuring via yield in the absence of via redundancy 有权
公开(公告)号：US10741489B2
公开(公告)日：2020-08-11
申请号：US13529583
申请日：2012-06-21
申请人： James Walter Blatchford
发明人： James Walter Blatchford
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/522 , H01L23/528 , H01L21/768
摘要： A rectangular via extending between interconnects in different metallization levels can have a planform with a width equal to the width of the interconnects and a length equal to twice the width and can be aligned along a long dimension with a length of the upper interconnect. In an integrated circuit layout, the planform can be centered over the width of the lower interconnect, allowing for misalignment during fabrication while maintaining a robust electrical connection. The bottom of the via may be aligned with an upper surface of the lower interconnect or may include portions below the lower interconnect's upper surface. Fewer adjacent routing tracks are blocked by use of the rectangular via than would be blocked using redundant square vias, while ensuring reliability of the electrical connection despite potential misalignment during fabrication.

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