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1. 发明授权

US09728619B2 Generation of multiple diameter nanowire field effect transistors 有权
公开(公告)号：US09728619B2
公开(公告)日：2017-08-08
申请号：US13610266
申请日：2012-09-11
申请人： Sarunya Bangsaruntip , Guy M. Cohen , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy M. Cohen , Jeffrey W. Sleight
IPC分类号： H01L29/423 , B82Y10/00 , H01L29/06 , H01L29/66 , H01L29/786
CPC分类号： H01L29/42392 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/66439 , H01L29/78696
摘要： A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming pairs of semiconductor pads connected via respective nanowire channels at each of first and second regions with different initial semiconductor thicknesses and reshaping the nanowire channels into nanowires to each have a respective differing thickness reflective of the different initial semiconductor thicknesses.

2. 发明授权

US09263276B2 High-k/metal gate transistor with L-shaped gate encapsulation layer 有权
公开(公告)号：US09263276B2
公开(公告)日：2016-02-16
申请号：US12551292
申请日：2009-11-18
申请人： Renee T. Mo , Wesley C. Natzle , Vijay Narayanan , Jeffrey W. Sleight
发明人： Renee T. Mo , Wesley C. Natzle , Vijay Narayanan , Jeffrey W. Sleight
IPC分类号： H01L29/78 , H01L21/28 , H01L29/49 , H01L29/51 , H01L29/66
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/517 , H01L29/6659 , H01L29/7833
摘要： A transistor is provided that includes a silicon layer with a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, an L shaped gate encapsulation layer disposed on sidewalls of the gate stack, and a spacer disposed above the horizontal portion of the gate encapsulation layer and adjacent to the vertical portion of the gate encapsulation layer. The gate stack has a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The gate encapsulation layer has a vertical portion covering the sidewalls of the first, second, and third layers of the gate stack and a horizontal portion covering a portion of the silicon layer that is adjacent to the gate stack.

3. 发明授权

US08921825B2 Nanowire field effect transistor device 有权
标题翻译：纳米线场效应晶体管器件
公开(公告)号：US08921825B2
公开(公告)日：2014-12-30
申请号：US13608089
申请日：2012-09-10
申请人： Sarunya Bangsaruntip , Guy M. Cohen , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy M. Cohen , Jeffrey W. Sleight
IPC分类号： H01L29/06 , H01L29/786 , H01L29/423 , B82Y10/00 , H01L29/66 , H01L29/775
CPC分类号： B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66545 , H01L29/775 , H01L29/78696 , Y10S977/938
摘要： A field effect transistor device includes a nanowire, a gate stack comprising a gate dielectric layer disposed on the nanowire, a gate conductor layer disposed on the dielectric layer and a substrate, and an active region including a sidewall contact portion disposed on the substrate adjacent to the gate stack, the side wall contact portion is electrically in contact with the nanowire.
摘要翻译：场效应晶体管器件包括纳米线，包括设置在纳米线上的栅极电介质层的栅极堆叠，设置在电介质层上的栅极导体层和衬底，以及包括设置在基板上的侧壁接触部分的有源区域，栅极堆叠，侧壁接触部分与纳米线电接触。

4. 发明授权

US08901659B2 Tapered nanowire structure with reduced off current 有权
标题翻译：锥形纳米线结构具有减小的截止电流
公开(公告)号：US08901659B2
公开(公告)日：2014-12-02
申请号：US13369375
申请日：2012-02-09
申请人： Jeffrey W. Sleight , Sarunya Bangsaruntip
发明人： Jeffrey W. Sleight , Sarunya Bangsaruntip
IPC分类号： H01L29/66
CPC分类号： H01L21/02603 , B82Y10/00 , B82Y40/00 , B82Y99/00 , H01L21/02664 , H01L29/0669 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/66818 , H01L29/775 , H01L29/78696
摘要： Non-planar semiconductor devices including at least one semiconductor nanowire having a tapered profile which widens from the source side of the device towards the drain side of the device are provided which have reduced gate to drain coupling and therefore reduced gate induced drain tunneling currents.
摘要翻译：提供了包括具有从器件的源极侧朝向器件的漏极侧变宽的锥形轮廓的至少一个半导体纳米线的非平面半导体器件，其具有减小的栅极到漏极耦合并因此减小栅极感应漏极隧穿电流。

5. 发明授权

US08878298B2 Multiple Vt field-effect transistor devices 有权
标题翻译：多Vt场效应晶体管器件
公开(公告)号：US08878298B2
公开(公告)日：2014-11-04
申请号：US13346165
申请日：2012-01-09
申请人： Josephine B. Chang , Leland Chang , Renee T. Mo , Vijay Narayanan , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Renee T. Mo , Vijay Narayanan , Jeffrey W. Sleight
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7856 , H01L29/66795
摘要： Multiple threshold voltage (Vt) field-effect transistor (FET) devices and techniques for the fabrication thereof are provided. In one aspect, a FET device is provided including a source region; a drain region; at least one channel interconnecting the source and drain regions; and a gate, surrounding at least a portion of the channel, configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate.
摘要翻译：提供了多阈值电压（Vt）场效应晶体管（FET）器件及其制造技术。一方面，提供一种FET器件，其包括源极区域; 漏区; 将源极和漏极区互连的至少一个沟道; 以及围绕通道的至少一部分的栅极，其被配置为具有多个阈值电压，这是由于至少一个带边缘金属选择性地放置在整个栅极上。

6. 发明授权

US08871576B2 Silicon nanotube MOSFET 有权
标题翻译：硅纳米管MOSFET
公开(公告)号：US08871576B2
公开(公告)日：2014-10-28
申请号：US13036292
申请日：2011-02-28
申请人： Daniel Tekleab , Hung H. Tran , Jeffrey W. Sleight , Dureseti Chidambarrao
发明人： Daniel Tekleab , Hung H. Tran , Jeffrey W. Sleight , Dureseti Chidambarrao
IPC分类号： H01L29/49 , H01L29/06 , B82Y10/00 , H01L29/775 , H01L29/66 , H01L29/78
CPC分类号： H01L29/78 , B82Y10/00 , H01L29/0676 , H01L29/66439 , H01L29/66666 , H01L29/775 , H01L29/7827
摘要： A nanotubular MOSFET device and a method of fabricating the same are used to extend device scaling roadmap while maintaining good short channel effects and providing competitive drive current. The nanotubular MOSFET device includes a concentric tubular inner and outer gate separated from each other by a tubular shaped epitaxially grown silicon layer, and a source and drain respectively separated by spacers surrounding the tubular inner and outer gates. The method of forming the nanotubular MOSFET device includes: forming on a substrate a cylindrical shaped Si layer; forming an outer gate surrounding the cylindrical Si layer and positioned between a bottom spacer and a top spacer; growing a silicon epitaxial layer on the top spacer adjacent to a portion of the cylindrical shaped Si layer; etching an inner portion of the cylindrical shaped Si forming a hollow cylinder; forming an inner spacer at the bottom of the inner cylinder; forming an inner gate by filling a portion of the hollow cylinder; forming a sidewall spacer adjacent to the inner gate; and etching a deep trench for accessing and contacting the outer gate and drain.
摘要翻译：纳米管MOSFET器件及其制造方法用于扩展器件缩放路线图，同时保持良好的短沟道效应并提供有竞争力的驱动电流。纳米管MOSFET器件包括通过管状外延生长硅层彼此分离的同心管状内部和外部栅极，以及分别由围绕管状内部和外部门的间隔开的源极和漏极。形成纳米管MOSFET器件的方法包括：在衬底上形成圆柱形的Si层; 形成围绕圆柱形Si层并位于底部间隔件和顶部间隔件之间的外部门; 在与圆柱形Si层的一部分相邻的顶部间隔上生长硅外延层; 蚀刻形成中空圆筒的圆柱形Si的内部; 在内筒的底部形成内隔板; 通过填充中空圆筒的一部分形成内门; 形成邻近所述内门的侧壁间隔物; 并蚀刻用于访问和接触外部栅极和漏极的深沟槽。

7. 发明授权

US08669167B1 Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices 有权
标题翻译：金属门功能工程技术可实现多个阈值电压FINFET器件
公开(公告)号：US08669167B1
公开(公告)日：2014-03-11
申请号：US13596687
申请日：2012-08-28
申请人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L27/092
CPC分类号： H01L27/1211 , H01L21/845
摘要： Techniques are provided for gate work function engineering in FIN FET devices using a work function setting material an amount of which is provided proportional to fin pitch. In one aspect, a method of fabricating a FIN FET device includes the following steps. A SOI wafer having a SOI layer over a BOX is provided. An oxide layer is formed over the SOI layer. A plurality of fins is patterned in the SOI layer and the oxide layer. An interfacial oxide is formed on the fins. A conformal gate dielectric layer, a conformal gate metal layer and a conformal work function setting material layer are deposited on the fins. A volume of the conformal gate metal layer and a volume of the conformal work function setting material layer deposited over the fins is proportional to a pitch of the fins. A FIN FET device is also provided.
摘要翻译：在Fin FET器件中提供栅极功能工程的技术，其功能设定材料的数量与翅片间距成正比。一方面，制造FIN FET器件的方法包括以下步骤。提供了在BOX上具有SOI层的SOI晶片。在SOI层上形成氧化物层。在SOI层和氧化物层中图案化多个翅片。翅片上形成界面氧化物。共形栅介电层，共形栅极金属层和共形功函数设定材料层沉积在散热片上。共形栅极金属层的体积和沉积在鳍片上的共形功函数设定材料层的体积与翅片的间距成正比。还提供了一种FIN FET器件。

8. 发明申请

US20140051213A1 Techniques for Metal Gate Work Function Engineering to Enable Multiple Threshold Voltage Nanowire FET Devices 有权
标题翻译：金属栅极工作功能工程技术开启多阈值电压纳米线FET器件
公开(公告)号：US20140051213A1
公开(公告)日：2014-02-20
申请号：US13588724
申请日：2012-08-17
申请人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L21/336
CPC分类号： H01L29/16 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/068 , H01L29/4232 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： A method of fabricating a nanowire FET device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. Nanowires and pads are etched in the SOI layer. The nanowires are suspended over the BOX. An interfacial oxide is formed surrounding each of the nanowires. A conformal gate dielectric is deposited on the interfacial oxide. A conformal first gate material is deposited on the conformal gate dielectric. A work function setting material is deposited on the conformal first gate material. A second gate material is deposited on the work function setting material to form at least one gate stack over the nanowires. A volume of the conformal first gate material and/or a volume of the work function setting material in the gate stack are/is proportional to a pitch of the nanowires.
摘要翻译：制造纳米线FET器件的方法包括以下步骤。提供了具有在BOX上的SOI层的SOI晶片。在SOI层中蚀刻纳米线和焊盘。纳米线悬挂在BOX上。围绕每个纳米线形成界面氧化物。共形栅电介质沉积在界面氧化物上。保形第一栅极材料沉积在保形栅极电介质上。工件功能设定材料沉积在保形第一栅极材料上。第二栅极材料沉积在功函数设定材料上以在纳米线上形成至少一个栅叠层。栅极堆叠中的共形第一栅极材料的体积和/或功函数设定材料的体积与纳米线的间距成比例。

9. 发明申请

US20140048882A1 TECHNIQUES FOR GATE WORKFUNCTION ENGINEERING TO REDUCE SHORT CHANNEL EFFECTS IN PLANAR CMOS DEVICES 有权
标题翻译：门工功能工程技术降低平面CMOS器件中的短路通道效应
公开(公告)号：US20140048882A1
公开(公告)日：2014-02-20
申请号：US13617283
申请日：2012-09-14
申请人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Isaac Lauer , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L29/78
CPC分类号： H01L29/66545 , H01L21/823842 , H01L21/82385 , H01L21/84 , H01L27/1203
摘要： In one aspect, a CMOS device is provided. The CMOS device includes a SOI wafer having a SOI layer over a BOX; one or more active areas formed in the SOI layer in which one or more FET devices are formed, each of the FET devices having an interfacial oxide on the SOI layer and a gate stack on the interfacial oxide layer, the gate stack having (i) a conformal gate dielectric layer present on a top and sides of the gate stack, (ii) a conformal gate metal layer lining the gate dielectric layer, and (iii) a conformal workfunction setting metal layer lining the conformal gate metal layer. A volume of the conformal gate metal layer and/or a volume of the conformal workfunction setting metal layer present in the gate stack are/is proportional to a length of the gate stack.
摘要翻译：在一个方面，提供一种CMOS器件。 CMOS器件包括在BOX上具有SOI层的SOI晶片; 形成在其中形成有一个或多个FET器件的SOI层中的一个或多个有源区，每个FET器件在SOI层上具有界面氧化物，在界面氧化物层上具有栅极堆叠，所述栅极堆叠具有（i）存在于栅极堆叠的顶部和侧面上的共形栅极电介质层，（ii）衬在栅极介电层的共形栅极金属层，以及（iii）在保形栅极金属层之上的共形功函数设定金属层。存在于栅极堆叠中的共形栅极金属层的体积和/或共形功函数设定金属层的体积与栅极堆叠的长度成比例。

10. 发明授权

US08648330B2 Nanowire field effect transistors 有权
标题翻译：纳米线场效应晶体管
公开(公告)号：US08648330B2
公开(公告)日：2014-02-11
申请号：US13343799
申请日：2012-01-05
申请人： Sarunya Bangsaruntip , Guy Cohen , Amlan Majumdar , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy Cohen , Amlan Majumdar , Jeffrey W. Sleight
IPC分类号： H01L27/12 , H01L21/335 , B82Y40/00 , B82Y99/00
CPC分类号： H01L29/42392 , B82Y10/00 , B82Y40/00 , H01L29/0673 , H01L29/068 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a substrate, forming a liner material around a portion of the nanowire, forming a capping layer on the liner material, forming a first spacer adjacent to sidewalls of the capping layer and around portions of the nanowire, forming a hardmask layer on the capping layer and the first spacer, removing an exposed portion of the nanowire to form a first cavity partially defined by the gate material, epitaxially growing a semiconductor material on an exposed cross section of the nanowire in the first cavity, removing the hardmask layer and the capping layer, forming a second capping layer around the semiconductor material epitaxially grown in the first cavity to define a channel region, and forming a source region and a drain region contacting the channel region.
摘要翻译：形成纳米线场效应晶体管（FET）器件的方法包括在衬底上形成纳米线，在纳米线的一部分周围形成衬垫材料，在衬垫材料上形成覆盖层，形成邻近覆盖层和纳米线的周围部分，在覆盖层和第一间隔物上形成硬掩模层，去除纳米线的暴露部分以形成由栅极材料部分限定的第一空腔，在暴露的杂交上外延生长半导体材料在所述第一空腔中的所述纳米线的截面，去除所述硬掩模层和所述覆盖层，在所述第一空腔中外延生长的所述半导体材料周围形成第二覆盖层，以限定沟道区，以及形成与所述第二覆盖层接触的源极区和漏极区渠道区域。

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