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1. 发明申请

US20140059328A1 MECHANISM FOR PERFORMING SPECULATIVE PREDICATED INSTRUCTIONS 有权
标题翻译：执行频谱预测指令的机制
公开(公告)号：US20140059328A1
公开(公告)日：2014-02-27
申请号：US13590870
申请日：2012-08-21
申请人： Jeffry E. Gonion
发明人： Jeffry E. Gonion
IPC分类号： G06F9/302
CPC分类号： G06F9/30036 , G06F9/30043 , G06F9/30072 , G06F9/3842 , G06F9/3859 , G06F9/3861
摘要： A mechanism for executing speculative predicated instructions may include execution of initiating execution of a vector instruction when one or more operands upon which the vector instruction depends are available for use, even if a predicate vector that the vector instruction also depends is not available. If the predicate vector was not available, the results of the execution of the vector instruction may be temporarily held until the predicate vector becomes available, at which time, a destination vector may be updated with the results.
摘要翻译：用于执行推测性预测指令的机制可以包括当向量指令所依赖的一个或多个操作数可用于使用时启动向量指令的执行的执行，即使该向量指令也依赖的谓词向量不可用。如果谓词向量不可用，则可以暂时保持向量指令的执行结果，直到谓词向量变得可用，此时可以用结果更新目的地向量。

2. 发明授权

US08356164B2 Shift-in-right instructions for processing vectors 有权
标题翻译：用于处理向量的右移指令
公开(公告)号：US08356164B2
公开(公告)日：2013-01-15
申请号：US12495643
申请日：2009-06-30
申请人： Jeffry E. Gonion , Keith E. Diefendorff
发明人： Jeffry E. Gonion , Keith E. Diefendorff
IPC分类号： G06F15/00 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F8/4441 , G06F9/3001 , G06F9/30036 , G06F9/30072 , G06F9/30076 , G06F9/3838 , G06F9/3887
摘要： The described embodiments provide a processor for generating a result vector with shifted values from an input vector. During operation, the processor receives an input vector and a control vector. Using these vectors, the processor generates the result vector, which can contain shifted values or propagated values from the input vector, depending on the value of the control vector. In addition, a predicate vector can be used to control the values that are written to the result vector.
摘要翻译：所描述的实施例提供了一种用于从输入向量生成具有移位值的结果向量的处理器。在操作期间，处理器接收输入向量和控制向量。使用这些向量，处理器根据控制向量的值生成结果向量，该向量可以包含来自输入向量的移位值或传播值。此外，谓词向量可以用于控制写入结果向量的值。

3. 发明申请

US20120331341A1 SCALAR READXF INSTRUCTION FOR POROCESSING VECTORS 有权
标题翻译：标准直读指令用于波导矢量
公开(公告)号：US20120331341A1
公开(公告)日：2012-12-27
申请号：US13604414
申请日：2012-09-05
申请人： Jeffry E. Gonion
发明人： Jeffry E. Gonion
IPC分类号： G06F11/00
CPC分类号： G06F8/4441 , G06F9/30036 , G06F9/30072 , G06F9/3865
摘要： The described embodiments include a processor that handles faults. The processor first receives an input vector, a control vector, and a predicate vector, each vector comprising a plurality of elements. Then, for a first element of the input vector for which corresponding elements of the control vector and the predicate vector are active, the processor performs a scalar read operation using an address from the element of the input vector. When a fault condition is encountered while performing the read operation, the processor determines if the element is a first element where a corresponding element of the control vector is active. If so (i.e., if the element is a first element where a corresponding element of the control vector is active), the processor processes the fault. Otherwise, the processor masks the fault for the element.
摘要翻译：所描述的实施例包括处理故障的处理器。处理器首先接收输入向量，控制向量和谓词向量，每个向量包括多个元素。然后，对于控制向量和谓词向量的相应元素有效的输入向量的第一元素，处理器使用来自输入向量的元素的地址来执行标量读操作。当执行读取操作时遇到故障条件时，处理器确定元件是否是控制向量的相应元件处于活动状态的第一元素。如果是（如果元件是控制向量的相应元件处于活动状态的第一个元件），则处理器处理故障。否则，处理器会屏蔽该元素的故障。

4. 发明授权

US08271832B2 Non-faulting and first-faulting instructions for processing vectors 有权
标题翻译：用于处理向量的无故障和第一故障指令
公开(公告)号：US08271832B2
公开(公告)日：2012-09-18
申请号：US12873063
申请日：2010-08-31
申请人： Jeffry E. Gonion , Keith E. Diefendorff
发明人： Jeffry E. Gonion , Keith E. Diefendorff
IPC分类号： G06F11/00
CPC分类号： G06F9/3861 , G06F8/4441 , G06F9/30036 , G06F9/30072
摘要： The described embodiments include a processor that handles faults during execution of a vector instruction. The processor starts by receiving a vector instruction that uses at least one vector of values that includes N elements as an input. In addition, the processor optionally receives a predicate vector that includes N elements. The processor then executes the vector instruction. In the described embodiments, when executing the vector instruction, if the predicate vector is received, for each element in the vector of values for which a corresponding element in the predicate vector is active, otherwise, for each element in the vector of values, the processor performs an operation for the vector instruction for the element in the vector of values. While performing the operation, the processor conditionally masks faults encountered (i.e., faults caused by an illegal operation).
摘要翻译：所描述的实施例包括在执行向量指令期间处理故障的处理器。处理器通过接收使用包含N个元素的至少一个值向量作为输入的向量指令开始。此外，处理器可选地接收包括N个元素的谓词向量。然后处理器执行向量指令。在所描述的实施例中，当执行向量指令时，如果接收到谓词向量，则对于谓词向量中的相应元素的值的矢量中的每个元素是活动的，否则，对于值向量中的每个元素，处理器对值向量中的元素执行向量指令的操作。在执行操作时，处理器有条件地掩盖遇到的故障（即由非法操作引起的故障）。

5. 发明申请

US20110320763A1 USING ADDRESSES TO DETECT OVERLAPPING MEMORY REGIONS 有权
标题翻译：使用地址来检测重写存储区域
公开(公告)号：US20110320763A1
公开(公告)日：2011-12-29
申请号：US13167633
申请日：2011-06-23
申请人： Jeffry E. Gonion
发明人： Jeffry E. Gonion
IPC分类号： G06F12/06
CPC分类号： G06F9/3834 , G06F9/3004
摘要： The described embodiments determine if two addressed memory regions overlap. First, a first address for a first memory region and a second address for a second memory region are received. Then a composite address is generated from the first and second addresses. Next, an upper subset and a lower subset of the bits in the addresses are determined. Then, using the upper and lower subsets of the addresses, a determination is made whether the addresses meet a condition from a set of conditions. If so, a determination is made whether the lower subset of the bits in the addresses meet a criteria from a set of criteria. Based on the determination whether the lower subset of the bits in the addresses meet a criteria, a determination is made whether the memory regions overlap or do not overlap.
摘要翻译：所描述的实施例确定两个寻址的存储器区域是否重叠。首先，接收第一存储区域的第一地址和第二存储器区域的第二地址。然后从第一和第二地址生成复合地址。接下来，确定地址中的位的上部子集和下部子集。然后，使用地址的上限和下限子集，确定地址是否满足一组条件的条件。如果是，则确定地址中的比特的较低子集是否符合一组标准的标准。基于确定地址中的比特的较低子集是否满足标准，确定存储器区域是重叠还是不重叠。

6. 发明申请

US20100235612A1 MACROSCALAR PROCESSOR ARCHITECTURE 有权
标题翻译：宏观处理器架构
公开(公告)号：US20100235612A1
公开(公告)日：2010-09-16
申请号：US12788250
申请日：2010-05-26
申请人： Jeffry E. Gonion
发明人： Jeffry E. Gonion
IPC分类号： G06F9/44 , G06F15/00
CPC分类号： G06F8/443 , G06F8/441
摘要： A macroscalar processor architecture is described herein. In one embodiment, an exemplary processor includes one or more execution units to execute instructions and one or more iteration units coupled to the execution units. The one or more iteration units receive one or more primary instructions of a program loop that comprise a machine executable program. For each of the primary instructions received, at least one of the iteration units generates multiple secondary instructions that correspond to multiple loop iterations of the task of the respective primary instruction when executed by the one or more execution units. Other methods and apparatuses are also described.
摘要翻译：这里描述了宏分级处理器架构。在一个实施例中，示例性处理器包括执行指令的一个或多个执行单元和耦合到执行单元的一个或多个迭代单元。一个或多个迭代单元接收包括机器可执行程序的程序循环的一个或多个主要指令。对于接收到的每个主要指令，当由一个或多个执行单元执行时，至少一个迭代单元产生对应于相应主指令的任务的多个循环迭代的多个辅助指令。还描述了其它方法和装置。

7. 发明申请

US20100079313A1 METHOD AND APPARATUS FOR COMPRESSING AND DECOMPRESSING DATA 失效
标题翻译：用于压缩和分解数据的方法和装置
公开(公告)号：US20100079313A1
公开(公告)日：2010-04-01
申请号：US12495568
申请日：2009-06-30
申请人： Jeffry E. Gonion
发明人： Jeffry E. Gonion
IPC分类号： H03M7/30
CPC分类号： H03M7/40
摘要： The described embodiments include a system for performing data compression. The system includes a compression mechanism with N channels, and an internal decompression mechanism in the compression mechanism that accepts N channels of fixed-length packets. The compression mechanism is configured to receive an input bit stream that includes a set of data words. In response to receiving a request from the internal decompression mechanism identifying at least one of the channels for which a fixed-length packet is to be appended to the output stream, the system fills a fixed-length packet for the identified channel with compressed data words; appends the fixed-length packet to the output stream; and forwards a copy of the fixed-length packet to the internal decompression mechanism. The internal decompression mechanism decompresses fixed-length packets for each of the channels to determine a next fixed-length packet to be appended to the output stream.
摘要翻译：所描述的实施例包括用于执行数据压缩的系统。该系统包括具有N个信道的压缩机制，并且在压缩机制中具有接收N个固定长度分组的信道的内部解压缩机制。压缩机构被配置为接收包括一组数据字的输入比特流。响应于接收到来自内部解压缩机制的请求，该请求标识要向其附加固定长度分组的信道中的至少一个信道，系统用压缩数据字填充所识别的信道的固定长度分组 ; 将固定长度的数据包附加到输出流; 并将固定长度分组的副本转发到内部解压缩机制。内部解压缩机制解压缩每个信道的固定长度分组，以确定要附加到输出流的下一个固定长度分组。

8. 发明申请

US20100077183A1 CONDITIONAL DATA-DEPENDENCY RESOLUTION IN VECTOR PROCESSORS 有权
标题翻译：矢量处理器中的条件数据依赖性分辨率
公开(公告)号：US20100077183A1
公开(公告)日：2010-03-25
申请号：US12237212
申请日：2008-09-24
申请人： Jeffry E. Gonion , Keith E. Diefendorff
发明人： Jeffry E. Gonion , Keith E. Diefendorff
IPC分类号： G06F9/30
CPC分类号： G06F9/30072 , G06F9/3887
摘要： Embodiments of a method for performing parallel operations in a computer system when one or more conditional dependencies may be present, where a given conditional dependency includes a dependency associated with at least two data elements based on a pair of conditions. During operation, a processor receives instructions for generating a vector of tracked positions of actual dependencies, where a given tracked position indicates the position of a given actual dependency, and where the given actual dependency occurs when the pair of condition matches one or more criteria. Then, the processor executes the instructions for generating the vector of tracked positions.
摘要翻译：当存在一个或多个条件依赖性时，在计算机系统中执行并行操作的方法的实施例，其中给定的条件依赖关系包括基于一对条件与至少两个数据元素相关联的依赖关系。在操作期间，处理器接收用于生成实际依赖性的跟踪位置的向量的指令，其中给定的跟踪位置指示给定实际依赖性的位置，并且当该对条件匹配一个或多个准则时发生给定的实际依赖性。然后，处理器执行用于生成跟踪位置的向量的指令。

9. 发明申请

US20100042817A1 SHIFT-IN-RIGHT INSTRUCTIONS FOR PROCESSING VECTORS 有权
标题翻译：适用于加工矢量的移动指令
公开(公告)号：US20100042817A1
公开(公告)日：2010-02-18
申请号：US12495643
申请日：2009-06-30
申请人： Jeffry E. Gonion , Keith E. Diefendorff
发明人： Jeffry E. Gonion , Keith E. Diefendorff
IPC分类号： G06F9/315 , G06F9/302
CPC分类号： G06F8/4441 , G06F9/3001 , G06F9/30036 , G06F9/30072 , G06F9/30076 , G06F9/3838 , G06F9/3887
摘要： The described embodiments provide a processor for generating a result vector with shifted values from an input vector. During operation, the processor receives an input vector and a control vector. Using these vectors, the processor generates the result vector, which can contain shifted values or propagated values from the input vector, depending on the value of the control vector. In addition, a predicate vector can be used to control the values that are written to the result vector.
摘要翻译：所描述的实施例提供了一种用于从输入向量生成具有移位值的结果向量的处理器。在操作期间，处理器接收输入向量和控制向量。使用这些向量，处理器根据控制向量的值生成结果向量，该向量可以包含来自输入向量的移位值或传播值。此外，谓词向量可以用于控制写入结果向量的值。

10. 发明申请

US20100042815A1 METHOD AND APPARATUS FOR EXECUTING PROGRAM CODE 有权
标题翻译：执行程序代码的方法和装置
公开(公告)号：US20100042815A1
公开(公告)日：2010-02-18
申请号：US12419629
申请日：2009-04-07
申请人： Jeffry E. Gonion , Keith E. Diefendorff
发明人： Jeffry E. Gonion , Keith E. Diefendorff
IPC分类号： G06F9/30 , G06F9/45
CPC分类号： G06F8/4441 , G06F9/3001 , G06F9/30036 , G06F9/30072 , G06F9/30076 , G06F9/3838 , G06F9/3887
摘要： The described embodiments provide a system that executes program code. While executing program code, the processor encounters at least one vector instruction and at least one vector-control instruction. The vector instruction includes a set of elements, wherein each element is used to perform an operation for a corresponding iteration of a loop in the program code. The vector-control instruction identifies elements in the vector instruction that may be operated on in parallel without causing an error due to a runtime data dependency between the iterations of the loop. The processor then executes the loop by repeatedly executing the vector-control instruction to identify a next group of elements that can be operated on in the vector instruction and selectively executing the vector instruction to perform the operation for the next group of elements in the vector instruction, until the operation has been performed for all elements of the vector instruction.
摘要翻译：所描述的实施例提供执行程序代码的系统。在执行程序代码时，处理器遇到至少一个向量指令和至少一个向量控制指令。向量指令包括一组元素，其中每个元素用于对程序代码中的循环的相应迭代执行操作。向量控制指令标识可以并行操作的向量指令中的元素，而不会由于循环的迭代之间的运行时数据依赖性而导致错误。然后，处理器通过重复执行矢量控制指令来执行循环，以识别可以在向量指令中操作的下一组元素，并且选择性地执行向量指令以执行向量指令中的下一组元素的操作，直到向量指令的所有元素执行操作为止。

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