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1. 发明授权

US07886245B2 Structure for optimizing the signal time behavior of an electronic circuit design 有权
标题翻译：用于优化电子电路设计的信号时间行为的结构
公开(公告)号：US07886245B2
公开(公告)日：2011-02-08
申请号：US12032734
申请日：2008-02-18
申请人： Guenther Hutzl , Stephan Held , Juergen Koehl , Bernhard Korte , Jens Massberg , Matthias Ringe , Jens Vygen
发明人： Guenther Hutzl , Stephan Held , Juergen Koehl , Bernhard Korte , Jens Massberg , Matthias Ringe , Jens Vygen
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/62 , G06F2217/84
摘要： A design structure for designing an electronic circuit, especially a clock tree and a sub-clock tree, within a set of sinks with given target arrival time windows, preferably on an integrated circuit designed by an IC design house or other circuit design provider. The clock tree and the sub-clock tree are preferably connected through one or multiple fixed circuits which must not be altered, cloned or removed. Several alternative implementations of the at least one logic structure are built and for each of the several alternative implementations data is stored. A set of configurations is built, each configuration comprising a combination of the one or several alternative implementations and each configuration satisfying the target arrival time windows at the complete set of sinks. A configuration is selected according to an evaluation of the data, preferably latency data, for constructing the configuration. No manual interaction is needed and a configuration with minimum latencies is provided.
摘要翻译：一种设计结构，用于设计具有给定目标到达时间窗口的一组接收器内的电子电路，特别是时钟树和子时钟树，优选地在由IC设计公司或其他电路设计提供商设计的集成电路上。时钟树和子时钟树优选通过一个或多个固定电路来连接，这些电路不能被改变，克隆或去除。构建至少一个逻辑结构的几个替代实施方案，并且为了存储数据的几个备选实现中的每一个。构建一组配置，每个配置包括一个或多个替代实现的组合，并且每个配置满足完整集合集合处的目标到达时间窗口。根据用于构造配置的数据（优选等待时间数据）的评估来选择配置。不需要手动交互，并提供具有最小延迟的配置。

2. 发明申请

US20080216042A1 Method and Computer System for Otimizing the Signal Time Behavior of an Electronic Circuit Design 有权
标题翻译：电子电路设计信号时间行为的方法和计算机系统
公开(公告)号：US20080216042A1
公开(公告)日：2008-09-04
申请号：US12032728
申请日：2008-02-18
申请人： Guenther Hutzl , Stephan Held , Juergen Koehl , Bernhard Korte , Jens Massberg , Matthias Ringe , Jens Vygen
发明人： Guenther Hutzl , Stephan Held , Juergen Koehl , Bernhard Korte , Jens Massberg , Matthias Ringe , Jens Vygen
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/62 , G06F2217/84
摘要： A method and program for designing an electronic circuit, especially a clock tree and a sub-clock tree, within a set of sinks with given target arrival time windows, preferably on an integrated circuit. The clock tree and the sub-clock tree are preferably connected through one or multiple fixed circuits which must not be altered, cloned or removed. Several alternative implementations of the at least one logic structure are built and for each of the several alternative implementations data is stored. A set of configurations is built, each configuration comprising a combination of the one or several alternative implementations and each configuration satisfying the target arrival time windows at the complete set of sinks. A configuration is selected according to an evaluation of the data, preferably latency data, for constructing the configuration. No manual interaction is needed and a configuration with minimum latencies is provided.
摘要翻译：一种用于设计具有给定的目标到达时间窗口的一组信宿中的电子电路，特别是时钟树和子时钟树的方法和程序，优选地在集成电路上。时钟树和子时钟树优选通过一个或多个固定电路来连接，这些电路不能被改变，克隆或去除。构建至少一个逻辑结构的几个替代实施方案，并且为了存储数据的几个备选实现中的每一个。构建一组配置，每个配置包括一个或多个替代实现的组合，并且每个配置满足完整集合集合处的目标到达时间窗口。根据用于构造配置的数据（优选等待时间数据）的评估来选择配置。不需要手动交互，并提供具有最小延迟的配置。

3. 发明授权

US07844931B2 Method and computer system for optimizing the signal time behavior of an electronic circuit design 有权
标题翻译：用于优化电子电路设计的信号时间行为的方法和计算机系统
公开(公告)号：US07844931B2
公开(公告)日：2010-11-30
申请号：US12032728
申请日：2008-02-18
申请人： Guenther Hutzl , Stephan Held , Juergen Koehl , Bernhard Korte , Jens Massberg , Matthias Ringe , Jens Vygen
发明人： Guenther Hutzl , Stephan Held , Juergen Koehl , Bernhard Korte , Jens Massberg , Matthias Ringe , Jens Vygen
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/62 , G06F2217/84
摘要： A method and program for designing an electronic circuit, especially a clock tree and a sub-clock tree, within a set of sinks with given target arrival time windows, preferably on an integrated circuit. The clock tree and the sub-clock tree are preferably connected through one or multiple fixed circuits which must not be altered, cloned or removed. Several alternative implementations of the at least one logic structure are built and for each of the several alternative implementations data is stored. A set of configurations is built, each configuration comprising a combination of the one or several alternative implementations and each configuration satisfying the target arrival time windows at the complete set of sinks. A configuration is selected according to an evaluation of the data, preferably latency data, for constructing the configuration. No manual interaction is needed and a configuration with minimum latencies is provided.
摘要翻译：一种用于设计具有给定的目标到达时间窗口的一组信宿中的电子电路，特别是时钟树和子时钟树的方法和程序，优选地在集成电路上。时钟树和子时钟树优选通过一个或多个固定电路来连接，这些电路不能被改变，克隆或去除。构建至少一个逻辑结构的几个替代实施方案，并且为了存储数据的几个备选实现中的每一个。构建一组配置，每个配置包括一个或多个替代实现的组合，并且每个配置满足完整集合集合处的目标到达时间窗口。根据用于构造配置的数据（优选等待时间数据）的评估来选择配置。不需要手动交互，并提供具有最小延迟的配置。

4. 发明申请

US20080216043A1 Structure for Optimizing the Signal Time Behavior of an Electronic Circuit Design 有权
标题翻译：用于优化电子电路设计的信号时间行为的结构
公开(公告)号：US20080216043A1
公开(公告)日：2008-09-04
申请号：US12032734
申请日：2008-02-18
申请人： Guenther Hutzl , Stephan Held , Juergen Koehl , Bernhard Korte , Jens Massberg , Matthias Ringe , Jens Vygen
发明人： Guenther Hutzl , Stephan Held , Juergen Koehl , Bernhard Korte , Jens Massberg , Matthias Ringe , Jens Vygen
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/62 , G06F2217/84
摘要： A design structure for designing an electronic circuit, especially a clock tree and a sub-clock tree, within a set of sinks with given target arrival time windows, preferably on an integrated circuit designed by an IC design house or other circuit design provider. The clock tree and the sub-clock tree are preferably connected through one or multiple fixed circuits which must not be altered, cloned or removed. Several alternative implementations of the at least one logic structure are built and for each of the several alternative implementations data is stored. A set of configurations is built, each configuration comprising a combination of the one or several alternative implementations and each configuration satisfying the target arrival time windows at the complete set of sinks. A configuration is selected according to an evaluation of the data, preferably latency data, for constructing the configuration. No manual interaction is needed and a configuration with minimum latencies is provided.
摘要翻译：一种设计结构，用于设计具有给定目标到达时间窗口的一组接收器内的电子电路，特别是时钟树和子时钟树，优选地在由IC设计公司或其他电路设计提供商设计的集成电路上。时钟树和子时钟树优选通过一个或多个固定电路来连接，这些电路不能被改变，克隆或去除。构建至少一个逻辑结构的几个替代实施方案，并且为了存储数据的几个备选实现中的每一个。构建一组配置，每个配置包括一个或多个替代实现的组合，并且每个配置满足完整集合集合处的目标到达时间窗口。根据用于构造配置的数据（优选等待时间数据）的评估来选择配置。不需要手动交互，并提供具有最小延迟的配置。

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