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1. 发明申请

US20100097091A1 Methodology for Bias Temperature Instability Test 失效
标题翻译：偏压温度不稳定性测试方法
公开(公告)号：US20100097091A1
公开(公告)日：2010-04-22
申请号：US12252904
申请日：2008-10-16
申请人： Jiaw-Ren Shih , Neeraj Kumar Jha , Rakesh Ranjan , Naresh Kumar Emani
发明人： Jiaw-Ren Shih , Neeraj Kumar Jha , Rakesh Ranjan , Naresh Kumar Emani
IPC分类号： G01R31/26
CPC分类号： G01R31/2874 , G01R31/2858
摘要： A method for performing a bias temperature instability test on a device includes performing a first stress on the device. After the first stress, a first measurement is performed to determine a first parameter of the device. After the first measurement, a second stress is performed on the device, wherein only the first parameter is measured between the first stress and the second stress. The method further includes performing a second measurement to determine a second parameter of the device after the second stress. The second parameter is different from the first parameter.
摘要翻译：用于对设备执行偏置温度不稳定性测试的方法包括在设备上执行第一应力。在第一次应力之后，进行第一次测量以确定该装置的第一个参数。在第一次测量之后，在该装置上执行第二应力，其中在第一应力和第二应力之间仅测量第一参数。该方法还包括执行第二测量以确定第二应力之后的装置的第二参数。第二个参数与第一个参数不同。

2. 发明授权

US07518192B2 Asymmetrical layout structure for ESD protection 有权
标题翻译： ESD保护的非对称布局结构
公开(公告)号：US07518192B2
公开(公告)日：2009-04-14
申请号：US10985532
申请日：2004-11-10
申请人： Kuo-Feng Yu , Jian-Hsing Lee , Jiaw-Ren Shih , Fu Chin Yang
发明人： Kuo-Feng Yu , Jian-Hsing Lee , Jiaw-Ren Shih , Fu Chin Yang
IPC分类号： H01L23/62
CPC分类号： H01L21/76816 , H01L27/0274 , H01L29/78
摘要： A semiconductor structure for electrostatic discharge protection is presented. The semiconductor structure comprises a grounded gate nMOS (GGNMOS) having a substrate, a gate electrode, a source region and a drain region. A plurality of contact plugs is formed on the source and drain side. A plurality of first level vias is electrically coupled to the GGNMOS and has a substantially asymmetrical layout in the source and drain regions. A second level via(s) re-routes the ESD current to the desired first level vias. The uniformity of the current flow in the GGNMOS is improved.
摘要翻译：提出了一种用于静电放电保护的半导体结构。半导体结构包括具有衬底，栅极电极，源极区域和漏极区域的接地栅极nMOS（GGNMOS）。在源极和漏极侧形成多个接触插塞。多个第一级通孔电耦合到GGNMOS并且在源极和漏极区域中具有基本不对称的布局。第二级通过将ESD电流重新路由到期望的第一级通孔。 GGNMOS中电流的均匀性得到改善。

3. 发明申请

US20080137244A1 Electrostatic discharge protection circuit 审中-公开
标题翻译：静电放电保护电路
公开(公告)号：US20080137244A1
公开(公告)日：2008-06-12
申请号：US11637108
申请日：2006-12-12
申请人： Kuo-Feng Yo , Jian-Hsing Lee , Jiaw-Ren Shih , Fu-Chin Yang
发明人： Kuo-Feng Yo , Jian-Hsing Lee , Jiaw-Ren Shih , Fu-Chin Yang
IPC分类号： H02H9/00
CPC分类号： H01L27/0262
摘要： An electrostatic discharge (ESD) protection circuit. The ESD protection circuit comprises a silicon controlled rectifier (SCR) device and a metal-oxide-semiconductor (MOS) triggering device. The SCR device has a cathode connected to a first fixed potential and an anode. The MOS triggering device has a gate and a source connected to the first fixed potential and a drain connected to the anode. In addition, the MOS triggering device is not physically disposed in the SCR device.
摘要翻译：静电放电（ESD）保护电路。 ESD保护电路包括可控硅整流器（SCR）器件和金属氧化物半导体（MOS）触发器件。 SCR器件具有连接到第一固定电位和阳极的阴极。 MOS触发装置具有连接到第一固定电位的栅极和源极以及连接到阳极的漏极。此外，MOS触发装置没有物理地设置在SCR装置中。

4. 发明授权

US06459127B1 Uniform current distribution SCR device for high voltage ESD protection 有权
标题翻译：均匀电流分配用于高压ESD保护的SCR器件
公开(公告)号：US06459127B1
公开(公告)日：2002-10-01
申请号：US10043793
申请日：2002-01-14
申请人： Jian-Hsing Lee , Kuo-Chio Liu , Bing-Lung Liao , Jiaw-Ren Shih
发明人： Jian-Hsing Lee , Kuo-Chio Liu , Bing-Lung Liao , Jiaw-Ren Shih
IPC分类号： H01L2362
CPC分类号： H01L27/0266
摘要： NMOS transistors for a high voltage process are protected from electrostatic discharge (ESD) by parasitic SCRs, where the two NMOS transistors and the two SCRs are designed to be in a completely symmetrical arrangement so that the currents in the components of the SCRs are completely uniform. This symmetry is achieved by adding a p+ diffusion to the source of one of the NMOS transistors. The added p+ diffusion guarantees that the resistance seen by both SCRs is identical. This insures even current distribution between both SCRs and thereby improves the high voltage characteristics of the ESD device.
摘要翻译：用于高电压工艺的NMOS晶体管通过寄生SCR防止静电放电（ESD），其中两个NMOS晶体管和两个SCR被设计为完全对称的布置，使得SCR的部件中的电流是完全均匀的。该对称性是通过向NMOS晶体管之一的源极添加p +扩散来实现的。添加的p +扩散保证两个SCR看到的电阻是相同的。这确保了两个SCR之间的均匀电流分布，从而改善了ESD器件的高电压特性。

5. 发明授权

US06437408B1 Plasma damage protection cell using floating N/P/N and P/N/P structure 有权
标题翻译：使用浮动N / P / N和P / N / P结构的等离子体损伤保护电池
公开(公告)号：US06437408B1
公开(公告)日：2002-08-20
申请号：US09904146
申请日：2001-07-13
申请人： Jiaw-Ren Shih , Shui-Hung Shen , Jian-Hsing Lee , Chrong Jung Lin
发明人： Jiaw-Ren Shih , Shui-Hung Shen , Jian-Hsing Lee , Chrong Jung Lin
IPC分类号： H01L2100
CPC分类号： H01L21/28123
摘要： A plasma damage protection cell using floating N/P/N and P/N/P structure, and a method to form the same are disclosed. Floating structures of the protection cell and the floating gates for the MOS devices are formed simultaneously on a semiconductor substrate having shallow trench isolation. The floating structures are implanted separately to form the N/P/N and P/N/P bipolar base, emitter and collector regions while the source/drain of the respective NMOS and PMOS devices are implanted with appropriate sequencing. The floating structures are connected to the substrate with appropriate polarity to provide protection at low leakage current levels and with tunable punch-through voltages.
摘要翻译：公开了使用浮动N / P / N和P / N / P结构的等离子体损伤保护单元及其形成方法。保护电池的浮动结构和用于MOS器件的浮置栅极同时形成在具有浅沟槽隔离的半导体衬底上。分别注入浮动结构以形成N / P / N和P / N / P双极基极，发射极和集电极区域，同时以适当的顺序植入各个NMOS和PMOS器件的源极/漏极。浮动结构以适当的极性连接到基板，以在低泄漏电流水平和可调穿通电压下提供保护。

6. 发明授权

US06323523B1 N-type structure for n-type pull-up and down I/O protection circuit 有权
标题翻译： N型结构用于n型上拉和下拉I / O保护电路
公开(公告)号：US06323523B1
公开(公告)日：2001-11-27
申请号：US09494682
申请日：2000-01-31
申请人： Jian-Hsing Lee , Yi-Hsun Wu , Shui-Hung Chen , Jiaw-Ren Shih
发明人： Jian-Hsing Lee , Yi-Hsun Wu , Shui-Hung Chen , Jiaw-Ren Shih
IPC分类号： H01L2362
CPC分类号： H01L27/0262 , H01L2924/0002 , H01L2924/00
摘要： An ESD protective circuit formed by n-type pull-up transistors and n-type pull-down transistors on a p-type silicon substrate for protecting an internal device circuit is disclosed. In the circuit, a n-well region having a p+ diffusion and a n+ diffusion therein being formed adjacent one drain region of one pull-up transistors, the p+ diffusion and a n+ diffusion, as well as all the drain regions of the pull-up transistors are coupled to a power supply. All the source regions of the pull-up transistors and drain regions of the pull-down transistors are connected to an I/O pad. All the source regions of the pull-down transistors including the p+ guardings are grounded. The gates of all transistors are connected to the internal device circuit so that the internal device circuit will be immunity from the ESD.
摘要翻译：公开了一种用于保护内部器件电路的p型硅衬底上的n型上拉晶体管和n型下拉晶体管形成的ESD保护电路。在该电路中，在一个上拉晶体管的一个漏极区附近形成有p +扩散和n +扩散的n阱区，p +扩散和n +扩散以及所述漏极区的所有漏极区，上拉晶体管耦合到电源。下拉晶体管的上拉晶体管和漏极区域的所有源极区域都连接到I / O焊盘。包括p +保护的下拉晶体管的所有源极区域接地。所有晶体管的栅极连接到内部器件电路，使得内部器件电路将免受ESD的影响。

7. 发明授权

US06277723B1 Plasma damage protection cell using floating N/P/N and P/N/P structure 有权
标题翻译：使用浮动N / P / N和P / N / P结构的等离子体损伤保护电池
公开(公告)号：US06277723B1
公开(公告)日：2001-08-21
申请号：US09418030
申请日：1999-10-14
申请人： Jiaw-Ren Shih , Shui-Hung Chen , Jian-Hsing Lee , Chrong Jung Lin
发明人： Jiaw-Ren Shih , Shui-Hung Chen , Jian-Hsing Lee , Chrong Jung Lin
IPC分类号： H01L2144
CPC分类号： H01L21/28123
摘要： A plasma damage protection cell using floating N/P/N and P/N/P structure, and a method to form the same are disclosed. Floating structures of the protection cell and the floating gates for the MOS devices are formed simultaneously on a semiconductor substrate having shallow trench isolation. The floating structures are implanted separately to form the N/P/N and P/N/P bipolar base, emitter and collector regions while the source/drain of the respective NMOS and PMOS devices are implanted with appropriate sequencing. The floating structures are connected to the substrate with appropriate polarity to provide protection at low leakage current levels and with tunable punch-through voltages.
摘要翻译：公开了使用浮动N / P / N和P / N / P结构的等离子体损伤保护单元及其形成方法。保护电池的浮动结构和用于MOS器件的浮置栅极同时形成在具有浅沟槽隔离的半导体衬底上。分别注入浮动结构以形成N / P / N和P / N / P双极基极，发射极和集电极区域，同时以适当的顺序植入各个NMOS和PMOS器件的源极/漏极。浮动结构以适当的极性连接到基板，以在低泄漏电流水平和可调穿通电压下提供保护。

8. 发明授权

US06235600B1 Method for improving hot carrier lifetime via a nitrogen implantation procedure performed before or after a teos liner deposition 有权
标题翻译：通过在硅橡胶衬垫沉积之前或之后进行的氮注入工艺改善热载流子寿命的方法
公开(公告)号：US06235600B1
公开(公告)日：2001-05-22
申请号：US09531403
申请日：2000-03-20
申请人： Mu-Chi Chiang , Hsien-Chin Lin , Jiaw-Ren Shih
发明人： Mu-Chi Chiang , Hsien-Chin Lin , Jiaw-Ren Shih
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/823418 , H01L21/823468 , H01L29/6656
摘要： A process for fabricating input/output, N channel, (I/O NMOS) devices, featuring an ion implanted nitrogen region, used to reduce hot carrier electron, (HEC), injection, has been developed. The process features implanting a nitorgen region, at the interface of an overlying silicon oxide layer, and an underlying lightly doped source/drain, (LDD), region. The implantation procedure can either be performed prior to, or after, the deposition of a silicon oxide liner layer, in both cases resulting in a desired nitrogen pile-up at the oxide-LDD interface, as well as resulting, in a more graded LDD profile. An increase in the time to fail, in regards to HCE injection, for these I/O NMOS devices, is realized, when compared to counterparts fabricated without the nitrogen implantation procedure.
摘要翻译：已经开发了用于制造用于减少热载流子电子（HEC）注入的具有离子注入氮区域的输入/输出N沟道（I / O NMOS）器件的工艺。该过程的特征是在覆盖的氧化硅层的界面和下面的轻掺杂源极/漏极（LDD）区域上注入nitorgen区域。在两种情况下，在氧化硅衬垫层的沉积之前或之后，可以进行注入工艺，导致在氧化物 - LDD界面处产生所需的氮堆积，以及在较梯度的LDD 个人资料当与没有氮气注入程序制造的对手相比时，实现了对于这些I / O NMOS器件，关于HCE注入的失败时间的增加。

9. 发明授权

US6122201A Clipped sine wave channel erase method to reduce oxide trapping charge generation rate of flash EEPROM 有权
标题翻译：缩短正弦波通道擦除方法，以减少闪存EEPROM的氧化物俘获电荷产生速率
公开(公告)号：US6122201A
公开(公告)日：2000-09-19
申请号：US421516
申请日：1999-10-20
申请人： Jian-Hsing Lee , Kuo-Reay Peng , Shui-Hung Chen , Jiaw-Ren Shih
发明人： Jian-Hsing Lee , Kuo-Reay Peng , Shui-Hung Chen , Jiaw-Ren Shih
IPC分类号： G11C16/16 , G11C16/04
CPC分类号： G11C16/16
摘要： A method to channel erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to channel erase a flash EEPROM cell begins by removing the charge from the floating gate of the flash EEPROM cell. The channel erasing consists of applying a relatively large clipped sinusoidal negative voltage pulse to the control gate of said EEPROM cell and concurrently applying a moderately large positive voltage pulse to a first diffusion region. At the same time a ground reference potential is applied to the semiconductor substrate, while the drain, the source and a second diffusion well are allowed to float.
摘要翻译：在快速EEPROM的隧道氧化物中捕获电荷的同时消除闪存EEPROM擦除数据的方法，以便在延长编程和擦除周期之后，保持编程阈值电压和擦除阈值电压的适当分离。通过从闪存EEPROM单元的浮动栅极去除电荷，开始通道擦除闪存EEPROM单元的方法。通道擦除包括将相对较大的限幅正弦负电压脉冲施加到所述EEPROM单元的控制栅极，同时向第一扩散区域施加适度大的正电压脉冲。同时，对半导体衬底施加接地参考电位，同时使漏极，源极和第二扩散阱浮动。

10. 发明授权

US08648592B2 Semiconductor device components and methods 有权
标题翻译：半导体器件组件和方法
公开(公告)号：US08648592B2
公开(公告)日：2014-02-11
申请号：US13231812
申请日：2011-09-13
申请人： Bi-Ling Lin , Jian-Hong Lin , Ming-Hong Hsieh , Lee-Der Chen , Jiaw-Ren Shih , Chwei-Ching Chiu
发明人： Bi-Ling Lin , Jian-Hong Lin , Ming-Hong Hsieh , Lee-Der Chen , Jiaw-Ren Shih , Chwei-Ching Chiu
IPC分类号： G01V3/00
CPC分类号： H01L23/5256 , G01R31/2853 , G01R31/2858 , G01R31/2884 , H01L22/34 , H01L23/522 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor device components and methods are disclosed. In one embodiment, a semiconductor device component includes a conductive segment having a first surface, a second surface opposite the first surface, a first end, and a second end opposite the first end. A first via is coupled to the second surface of the conductive segment at the first end. A second via is coupled to the first surface of the conductive segment at the second end, and a third via is coupled to the second surface of the conductive segment at the second end.
摘要翻译：公开了半导体器件组件和方法。在一个实施例中，半导体器件部件包括具有第一表面，与第一表面相对的第二表面，第一端和与第一端相对的第二端的导电段。第一通孔在第一端耦合到导电段的第二表面。第二通孔在第二端处耦合到导电段的第一表面，并且第三通孔在第二端耦合到导电段的第二表面。

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