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1. 发明授权

US08539305B2 Semiconductor apparatus and data processing method 失效
标题翻译：半导体装置及数据处理方法
公开(公告)号：US08539305B2
公开(公告)日：2013-09-17
申请号：US13099395
申请日：2011-05-03
申请人： Jin Yeong Moon
发明人： Jin Yeong Moon
IPC分类号： H03M13/09 , H03M13/33
CPC分类号： H04L1/0061
摘要： A semiconductor apparatus includes a bus inversion information (DBI) processing unit configured to, when receiving multi-bit data, calculating DBI information of the data, and outputting a plurality of DBI flag signals, generate the plurality of DBI flag signals such that each DBI flag signal reflects DBI information of predetermined bits of the data, a first CRC processing unit configured to calculate cyclic redundancy check (CRC) information using the multi-bit data and partial DBI flag signals calculated among the plurality of DBI flag signals and output a plurality of CRC signals, and a second CRC processing unit configured to output CRC codes using the plurality of CRC signals and remaining DBI flag signals calculated among the plurality of the DBI flag signals.
摘要翻译：一种半导体装置，包括：总线反转信息（DBI）处理单元，被配置为当接收到多位数据时，计算数据的DBI信息，并输出多个DBI标志信号，生成多个DBI标志信号，使得每个DBI 标志信号反映数据的预定比特的DBI信息;第一CRC处理单元，被配置为使用在多个DBI标志信号中计算的多位数据和部分DBI标志信号来计算循环冗余校验（CRC）信息，并输出多个以及第二CRC处理单元，被配置为使用多个CRC信号和在多个DBI标志信号之间计算的剩余DBI标志信号来输出CRC码。

2. 发明申请

US20100329056A1 SENSE AMPLIFIER AND SEMICONDUCTOR INTEGRATED CIRCUIT USING THE SAME 有权
标题翻译：使用相同的SENSE放大器和半导体集成电路
公开(公告)号：US20100329056A1
公开(公告)日：2010-12-30
申请号：US12648340
申请日：2009-12-29
申请人： Jin Yeong MOON
发明人： Jin Yeong MOON
IPC分类号： G11C7/00 , G11C7/02
CPC分类号： G11C11/4094 , G11C7/02 , G11C7/08 , G11C7/12 , G11C11/4091
摘要： A sense amplifier resistant to malfunctions associated with offsets in inverter pairs is presented. The sense amplifier includes inverter pairs and a controller. Any one input terminal of the inverter pairs is electrically connected to a bit line and the other one input terminal is electrically connected to a /bit line. The controller is configured to precharge the bit line and the /bit line to a level corresponding to an offset of the inverter pairs in response to a first control signal. The controller senses a voltage difference of the bit line and the /bit line using the inverter pairs by connecting output terminals of the inverter pairs to the bit line pairs in response to a second control signal.
摘要翻译：提出了一种抵抗与逆变器对中的偏移相关的故障的感测放大器。感测放大器包括逆变器对和控制器。逆变器对的任何一个输入端子电连接到位线，而另一个输入端子电连接到/位线。控制器被配置为响应于第一控制信号将位线和/位线预充电到与逆变器对的偏移相对应的电平。响应于第二控制信号，控制器通过将反相器对的输出端连接到位线对来检测位线和/位线的电压差。

3. 发明授权

US07843219B2 XOR logic circuit 有权
标题翻译：异或逻辑电路
公开(公告)号：US07843219B2
公开(公告)日：2010-11-30
申请号：US12345751
申请日：2008-12-30
申请人： Jin-Yeong Moon
发明人： Jin-Yeong Moon
IPC分类号： G06F7/50 , H03K19/21
CPC分类号： H03K19/215
摘要： An XOR logic circuit includes a first transfer unit configured to transfer a logic high level data to an output terminal in response to data applied to first and second input terminals; a multiplexing unit configured to output a power voltage or a ground voltage in response to the data applied to the first and second input terminals; and a second transfer unit configured to transfer a logic low level data to the output terminal in response to an output signal of the multiplexing unit and the data applied to the first and second input terminals.
摘要翻译： XOR逻辑电路包括：第一传送单元，被配置为响应于施加到第一和第二输入端的数据将逻辑高电平数据传送到输出端; 复用单元，被配置为响应于施加到第一和第二输入端子的数据而输出电源电压或接地电压; 以及第二传送单元，其被配置为响应于所述多路复用单元的输出信号和施加到所述第一和第二输入端子的数据而将逻辑低电平数据传送到所述输出端子。

4. 发明申请

US20100141299A1 XOR LOGIC CIRCUIT 有权
标题翻译：异或逻辑电路
公开(公告)号：US20100141299A1
公开(公告)日：2010-06-10
申请号：US12345751
申请日：2008-12-30
申请人： Jin-Yeong MOON
发明人： Jin-Yeong MOON
IPC分类号： H03K19/21
CPC分类号： H03K19/215
摘要： An XOR logic circuit includes a first transfer unit configured to transfer a logic high level data to an output terminal in response to data applied to first and second input terminals; a multiplexing unit configured to output a power voltage or a ground voltage in response to the data applied to the first and second input terminals; and a second transfer unit configured to transfer a logic low level data to the output terminal in response to an output signal of the multiplexing unit and the data applied to the first and second input terminals.
摘要翻译： XOR逻辑电路包括：第一传送单元，被配置为响应于施加到第一和第二输入端的数据将逻辑高电平数据传送到输出端; 复用单元，被配置为响应于施加到第一和第二输入端子的数据而输出电源电压或接地电压; 以及第二传送单元，其被配置为响应于所述多路复用单元的输出信号和施加到所述第一和第二输入端子的数据而将逻辑低电平数据传送到所述输出端子。

5. 发明申请

US20120221927A1 SEMICONDUCTOR APPARATUS AND DATA PROCESSING METHOD 失效
标题翻译：半导体器件和数据处理方法
公开(公告)号：US20120221927A1
公开(公告)日：2012-08-30
申请号：US13099395
申请日：2011-05-03
申请人： Jin Yeong MOON
发明人： Jin Yeong MOON
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： H04L1/0061
摘要： A semiconductor apparatus includes a bus inversion information (DBI) processing unit configured to, when receiving multi-bit data, calculating DBI information of the data, and outputting a plurality of DBI flag signals, generate the plurality of DBI flag signals such that each DBI flag signal reflects DBI information of predetermined bits of the data, a first CRC processing unit configured to calculate cyclic redundancy check (CRC) information using the multi-bit data and partial DBI flag signals calculated among the plurality of DBI flag signals and output a plurality of CRC signals, and a second CRC processing unit configured to output CRC codes using the plurality of CRC signals and remaining DBI flag signals calculated among the plurality of the DBI flag signals.
摘要翻译：一种半导体装置，包括：总线反转信息（DBI）处理单元，被配置为当接收到多位数据时，计算数据的DBI信息，并输出多个DBI标志信号，生成多个DBI标志信号，使得每个DBI 标志信号反映数据的预定比特的DBI信息;第一CRC处理单元，被配置为使用在多个DBI标志信号中计算的多位数据和部分DBI标志信号来计算循环冗余校验（CRC）信息，并输出多个以及第二CRC处理单元，被配置为使用多个CRC信号和在多个DBI标志信号之间计算的剩余DBI标志信号来输出CRC码。

6. 发明授权

US08233343B2 Sense amplifier and semiconductor integrated circuit using the same 有权
标题翻译：感应放大器和半导体集成电路使用相同
公开(公告)号：US08233343B2
公开(公告)日：2012-07-31
申请号：US12648340
申请日：2009-12-29
申请人： Jin Yeong Moon
发明人： Jin Yeong Moon
IPC分类号： G11C7/00 , G11C7/02
CPC分类号： G11C11/4094 , G11C7/02 , G11C7/08 , G11C7/12 , G11C11/4091
摘要： A sense amplifier resistant to malfunctions associated with offsets in inverter pairs is presented. The sense amplifier includes inverter pairs and a controller. Any one input terminal of the inverter pairs is electrically connected to a bit line and the other one input terminal is electrically connected to a /bit line. The controller is configured to precharge the bit line and the /bit line to a level corresponding to an offset of the inverter pairs in response to a first control signal. The controller senses a voltage difference of the bit line and the /bit line using the inverter pairs by connecting output terminals of the inverter pairs to the bit line pairs in response to a second control signal.
摘要翻译：提出了一种抵抗与逆变器对中的偏移相关的故障的感测放大器。感测放大器包括逆变器对和控制器。逆变器对的任何一个输入端子电连接到位线，而另一个输入端子电连接到/位线。控制器被配置为响应于第一控制信号将位线和/位线预充电到与逆变器对的偏移相对应的电平。响应于第二控制信号，控制器通过将反相器对的输出端连接到位线对来检测位线和/位线的电压差。

7. 发明授权

US07755390B2 XOR logic circuit 有权
公开(公告)号：US07755390B2
公开(公告)日：2010-07-13
申请号：US12345751
申请日：2008-12-30
申请人： Jin-Yeong Moon
发明人： Jin-Yeong Moon
IPC分类号： G06F7/50 , H03K19/21
摘要： An XOR logic circuit includes a first transfer unit configured to transfer a logic high level data to an output terminal in response to data applied to first and second input terminals; a multiplexing unit configured to output a power voltage or a ground voltage in response to the data applied to the first and second input terminals; and a second transfer unit configured to transfer a logic low level data to the output terminal in response to an output signal of the multiplexing unit and the data applied to the first and second input terminals.

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