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1. 发明授权

US07725871B1 SAT-based technology mapping framework 有权
标题翻译：基于SAT的技术映射框架
公开(公告)号：US07725871B1
公开(公告)日：2010-05-25
申请号：US12123396
申请日：2008-05-19
申请人： Sean A. Safarpour , Gregg William Baeckler , Jinyong Yuan
发明人： Sean A. Safarpour , Gregg William Baeckler , Jinyong Yuan
IPC分类号： G06F17/50 , H03K19/00
CPC分类号： G06F17/5027
摘要： Valid implementations of functions with programmable logic blocks are efficiently determined by creating an approximation of a hardware configuration of programmable logic blocks to quickly screen out configurations unlikely to provide a valid results. If a configuration passes this first phase, the approximation is refined to search for valid function implementations with the hardware configuration. The approximation and refinement may use a partitioning of function input variables to logic blocks to reduce the search space. Additional conflict clauses may be used to further reduce the search space. Implementations of sample functions or other previously considered functions may be analyzed to identify conflict clauses that are reusable for analyzing other functions. A representation of potential implementations of a function can be subdivided into subsets and analyzed separately. The intersection of the solutions from each subset are valid implementations of the function.
摘要翻译：通过创建可编程逻辑块的硬件配置的近似来快速地筛选不太可能提供有效结果的配置来有效地确定具有可编程逻辑块的功能的有效实现。如果配置通过此第一阶段，则会对该近似进行细化，以便通过硬件配置搜索有效的功能实现。近似和细化可以使用功能输入变量对逻辑块的划分来减少搜索空间。可以使用额外的冲突条款来进一步减少搜索空间。可以分析样本函数或其他以前考虑的函数的实现，以识别可重用于分析其他函数的冲突条款。功能的潜在实现的表示可以细分为子集并分开分析。来自每个子集的解的交集是函数的有效实现。

2. 发明授权

US07397726B1 Flexible RAM clock enable 失效
标题翻译：灵活的RAM时钟使能
公开(公告)号：US07397726B1
公开(公告)日：2008-07-08
申请号：US11399771
申请日：2006-04-07
申请人： Jinyong Yuan , Christopher F. Lane , David E. Jefferson , Vaughn Betz
发明人： Jinyong Yuan , Christopher F. Lane , David E. Jefferson , Vaughn Betz
IPC分类号： G11C8/00 , G11C7/10
CPC分类号： G11C7/1075 , G11C8/18 , H03K19/1737
摘要： A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. The first set of configuration logic is also configurable to provide a first port core clock signal for controlling the memory block core. The first port core clock signal can either be the same as the first port input clock signal, or can be controlled independently from the first port input clock signal. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block. The second set of configuration logic is also configurable to provide a second port core clock signal for controlling the memory block core. The second port core clock signal can be controlled independently from the second port input clock signal.
摘要翻译：第一组配置逻辑可配置为提供用于控制存储器块的第一端口的输入寄存器的第一端口输入时钟信号。第一组配置逻辑也可配置为提供用于控制存储块核心的第一端口核心时钟信号。第一个端口核心时钟信号可以与第一个端口输入时钟信号相同，也可以独立于第一个端口输入时钟信号进行控制。第二组配置逻辑可配置为提供用于控制存储器块的第二端口的输入寄存器的第二端口输入时钟信号。第二组配置逻辑也可配置为提供用于控制存储块核心的第二端口核心时钟信号。可以独立于第二端口输入时钟信号来控制第二端口核心时钟信号。

3. 发明授权

US07249329B1 Technology mapping techniques for incomplete lookup tables 有权
标题翻译：用于不完整查询表的技术映射技术
公开(公告)号：US07249329B1
公开(公告)日：2007-07-24
申请号：US10859325
申请日：2004-06-01
申请人： Gregg William Baeckler , Jinyong Yuan , David W. Mendel
发明人： Gregg William Baeckler , Jinyong Yuan , David W. Mendel
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/505 , Y02T10/82
摘要： Technology mapping techniques for determining whether a function can be implemented using an incomplete lookup table (LUT) are provided. For example, the output of a function is compared to the output of an incomplete LUT for each binary value of the function's input signals and for each binary value of the bits stored in the incomplete LUT. For a LUT that is functionally asymmetric, the process can be repeated for multiple permutations of the input signals with respect to the input terminals of the LUT. As another example, the user function is converted into a network of multiplexers and complete LUTs, which are analyzed to determine if an incomplete LUT can implement the function. As another example, a truth table is constructed for a function. The truth table variables are then tested one by one as candidates for each input position using co-factoring and dependency checking.
摘要翻译：提供了用于确定是否可以使用不完整查找表（LUT）来实现功能的技术映射技术。例如，将函数的输出与功能输入信号的每个二进制值的不完整LUT的输出以及存储在不完全LUT中的位的每个二进制值进行比较。对于功能不对称的LUT，相对于LUT的输入端，可以重复进行输入信号的多个排列的处理。作为另一示例，用户功能被转换为多路复用器和完整LUT的网络，其被分析以确定不完整的LUT是否可以实现该功能。作为另一示例，为功能构建真值表。然后，将真值表变量逐个测试作为每个输入位置的候选，使用协同因子和依赖性检查。

4. 发明授权

US07246339B2 Methods for creating and expanding libraries of structured ASIC logic and other functions 失效
标题翻译：用于创建和扩展结构化ASIC逻辑和其他功能库的方法
公开(公告)号：US07246339B2
公开(公告)日：2007-07-17
申请号：US11101949
申请日：2005-04-08
申请人： Jinyong Yuan , Kar Keng Chua , Ji Park
发明人： Jinyong Yuan , Kar Keng Chua , Ji Park
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： G06F17/5045
摘要： Structured ASICs that are equivalent to FPGA logic designs are produced by making use of a library of known structured ASIC equivalents to FPGA logic functions. Such a library is expanded by a process that searches new FPGA logic designs for logic functions that either do not already have structured ASIC equivalents in the library or for which possibly improved structured ASIC equivalents can now be devised. The new and/or improved structured ASIC equivalents are added to the library, preferably with version information in the case of FPGA logic functions for which more than one structured ASIC equivalent is known.
摘要翻译：与FPGA逻辑设计相当的结构化ASIC通过利用FPGA逻辑功能的已知结构化ASIC等效的库来产生。这样一个库可以通过一个过程来扩展，该过程可以搜索逻辑功能的新FPGA逻辑设计，这些逻辑功能在库中尚未具有结构化ASIC等价物，或者现在可以设计出可能改进的结构化ASIC等价物。新的和/或改进的结构化ASIC等效物被添加到库中，优选地在FPGA逻辑功能的情况下具有已知多于一个结构化ASIC等效物的版本信息。

5. 发明授权

US07126858B1 Apparatus for emulating asynchronous clear in memory structure and method for implementing the same 有权
标题翻译：用于模拟异步清除存储器结构的装置及其实现方法
公开(公告)号：US07126858B1
公开(公告)日：2006-10-24
申请号：US11156083
申请日：2005-06-17
申请人： Jinyong Yuan , Peter Kazarian
发明人： Jinyong Yuan , Peter Kazarian
IPC分类号： G11C7/10
CPC分类号： G11C7/22
摘要： Circuitry is disclosed for emulating asynchronous clear on each of a read address register of a memory cell and a data output register of a memory cell such that the memory cell can be defined in a memory structure that does not support asynchronous clear capability. The emulation includes defining the memory cell to have a registered read address input and a data output connected to an input of a multiplexer. The register connected to the read address input of the multiplexer does not include an asynchronous clear connection. The data transmitted from the memory cell to the multiplexer is output from the multiplexer when an asynchronous clear signal has not been asserted. However, the multiplexer is further connected to output either null data or a ground signal in lieu of the data transmitted from the memory cell when an asynchronous clear signal has been asserted.
摘要翻译：公开了用于在存储器单元的读地址寄存器和存储器单元的数据输出寄存器中的每一个上模拟异步清零的电路，使得可以在不支持异步清除能力的存储器结构中定义存储器单元。仿真包括定义存储器单元以具有注册的读取地址输入和连接到多路复用器的输入的数据输出。连接到多路复用器的读地址输入的寄存器不包括异步清除连接。当异步清除信号尚未被断言时，从存储器单元发送到多路复用器的数据被从复用器输出。然而，当异步清除信号被断言时，多路复用器进一步连接以输出空数据或接地信号来代替从存储器单元发送的数据。

6. 发明授权

US08006206B1 Gated clock conversion 有权
标题翻译：门控时钟转换
公开(公告)号：US08006206B1
公开(公告)日：2011-08-23
申请号：US12174632
申请日：2008-07-17
申请人： Jinyong Yuan
发明人： Jinyong Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F2217/62
摘要： Gated clock signals in ASIC designs are automatically optimized for implementation with a programmable device. Components having gated clock signals are identified and converted to operate directly from the base clock signal. To maintain compatibility, the data signal to the component is modified to connect with additional input logic responsive to a clock enable signal. The input logic modifies the signal received by the component's data input so that the component's output in response to the clock enable signal is unchanged. To this end, a system and method may identify the logic cone associated with a gated clock signal, convert this logic cone into a Boolean expression, and determine cofactors of the base clock signal from this Boolean expression. The input logic and clock enable logic are derived from an analysis of the cofactors of the base clock signal.
摘要翻译：自动优化ASIC设计中的门控时钟信号，以实现可编程器件。具有门控时钟信号的部件被识别并转换成从基本时钟信号直接操作。为了保持兼容性，修改组件的数据信号以响应于时钟使能信号与附加的输入逻辑连接。输入逻辑修改由组件的数据输入接收到的信号，使得响应时钟使能信号的组件输出不变。为此，系统和方法可以识别与门控时钟信号相关联的逻辑锥，将该逻辑锥转换为布尔表达式，并且从该布尔表达式确定基本时钟信号的辅因子。输入逻辑和时钟使能逻辑是从基本时钟信号的辅因子的分析得出的。

7. 发明授权

US07587688B1 User-directed timing-driven synthesis 有权
标题翻译：用户导向的定时驱动综合
公开(公告)号：US07587688B1
公开(公告)日：2009-09-08
申请号：US11510206
申请日：2006-08-24
申请人： Babette Van Antwerpen , Jinyong Yuan , David Karchmer
发明人： Babette Van Antwerpen , Jinyong Yuan , David Karchmer
IPC分类号： G06F17/20
CPC分类号： G06F17/5045
摘要： Users or applications provide optimization information that specifies performance-critical portions of the design. Users can identify performance-critical portions of their designs from a priori evaluation of their design or by analyzing the results of previous compilations of their design or similar designs. An application may extract and analyze performance information from previous compilations of the design or similar designs to automatically specify the performance-critical portions of the design. The compilation software uses this specification to focus the appropriate types and amount of optimization on different portions of the design. The compilation software may use additional optimization techniques and/or may allocate additional computing resources to optimize the performance of performance-critical portions of the design. Other portions of the design that are not performance-critical may be optimized using balanced optimization techniques. Portions of the design may be designated as critical with respect to timing, area, power consumption or any other performance aspect.
摘要翻译：用户或应用程序提供了指定设计的性能关键部分的优化信息。用户可以从其设计的先验评估或通过分析其设计或类似设计的以前编译的结果来识别其设计中的性能关键部分。应用程序可以从以前的设计或类似设计的编译中提取和分析性能信息，以自动指定设计的性能关键部分。编译软件使用此规范将适当的类型和数量的优化集中在设计的不同部分。编译软件可以使用额外的优化技术和/或可以分配额外的计算资源来优化设计的性能关键部分的性能。可以使用平衡优化技术优化设计中不具有性能关键性的其他部分。关于时间，面积，功耗或任何其他性能方面，设计的部分可能被指定为关键。

8. 发明申请

US20080253220A1 Flexible RAM Clock Enable 有权
标题翻译：灵活的RAM时钟使能
公开(公告)号：US20080253220A1
公开(公告)日：2008-10-16
申请号：US12145440
申请日：2008-06-24
申请人： Jinyong Yuan , Christopher F. Lane , David E. Jefferson , Vaughn Betz
发明人： Jinyong Yuan , Christopher F. Lane , David E. Jefferson , Vaughn Betz
IPC分类号： G11C8/18
CPC分类号： G11C7/1075 , G11C8/18 , H03K19/1737
摘要： A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block.
摘要翻译：第一组配置逻辑可配置为提供用于控制存储器块的第一端口的输入寄存器的第一端口输入时钟信号。第二组配置逻辑可配置为提供用于控制存储器块的第二端口的输入寄存器的第二端口输入时钟信号。

9. 发明授权

US07415693B1 Method and apparatus for reducing synthesis runtime 有权
标题翻译：减少合成运行时间的方法和装置
公开(公告)号：US07415693B1
公开(公告)日：2008-08-19
申请号：US10851355
申请日：2004-05-21
申请人： Babette van Antwerpen , Gregg William Baeckler , Jinyong Yuan
发明人： Babette van Antwerpen , Gregg William Baeckler , Jinyong Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method for designing a system includes caching a representation of a first subnet with a synthesis result of the first subnet. The synthesis result of the first subnet is utilized for a second subnet in response to determining that a representation of the second subnet is identical to the representation of the first subnet.
摘要翻译：一种用于设计系统的方法包括用第一子网的综合结果来缓存第一子网的表示。响应于确定第二子网的表示与第一子网的表示相同，第一子网的综合结果被用于第二子网。

10. 发明授权

US07406668B1 Methods for producing mappings of logic suitable for FPGA and structured ASIC implementations 失效
标题翻译：用于生成适用于FPGA和结构化ASIC实现的逻辑映射的方法
公开(公告)号：US07406668B1
公开(公告)日：2008-07-29
申请号：US11072560
申请日：2005-03-03
申请人： Bruce Pedersen , Jinyong Yuan
发明人： Bruce Pedersen , Jinyong Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Implementation of a logic design in either an FPGA or a structured ASIC is facilitated by designing either type of implementation so that it takes into account the possible need to migrate the design to the other type of implementation. Portions of the design that are being considered for one type of implementation (e.g., FPGA implementation) are assessed for suitability and/or desirability based not only on their suitability/desirability in that one type of implementation, but also based on their suitability/desirability in the other type of implementation (e.g., structured ASIC implementation).
摘要翻译：通过设计任何一种实现方式来实现FPGA或结构化ASIC中的逻辑设计，从而考虑到可能需要将设计迁移到其他类型的实现。根据其适用性/适用性，还可以根据其适用性/可取性评估正在考虑用于一种类型实现的部分（例如，FPGA实现）的适用性和/或可取性。在其他类型的实现（例如，结构化ASIC实现）中。

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