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1. 发明申请

US20130054938A1 EFFICIENT PIPELINE PARALLELISM USING FRAME SHARED MEMORY 有权
标题翻译：使用框架共享存储器的有效管道并行列表
公开(公告)号：US20130054938A1
公开(公告)日：2013-02-28
申请号：US13590307
申请日：2012-08-21
申请人： John Giacomoni , Manish Vachharajani
发明人： John Giacomoni , Manish Vachharajani
IPC分类号： G06F15/76
CPC分类号： G06F12/0846 , G06F9/544 , G06F12/0806 , G06F12/128
摘要： A systems and methods are disclosed that provide an efficient parallel pipeline for data processing using a multi-core processor. Embodiments allocate a shared memory portion of the memory that is accessible from more than one context of execution and/or process a frame in a plurality of processing stages processed by a context of execution. In some embodiments, each of the plurality of processing stages may be bound to a processing core of the multi-core processor. In other embodiments include one or more processing stages with a point-to-point communication mechanism that operates in shared memory.
摘要翻译：公开了一种提供用于使用多核处理器的数据处理的有效的并行流水线的系统和方法。实施例分配存储器的共享存储器部分，其可由多于一个执行上下文访问和/或处理由执行上下文处理的多个处理阶段中的帧。在一些实施例中，多个处理级中的每一个可以被绑定到多核处理器的处理核心。在其他实施例中，包括具有在共享存储器中操作的点对点通信机制的一个或多个处理级。

2. 发明授权

US08112594B2 Efficient point-to-point enqueue and dequeue communications 有权
标题翻译：高效的点对点入队和出队通信
公开(公告)号：US08112594B2
公开(公告)日：2012-02-07
申请号：US12106712
申请日：2008-04-21
申请人： John Giacomoni , Manish Vachharajani
发明人： John Giacomoni , Manish Vachharajani
IPC分类号： G06F12/00
CPC分类号： G06F12/0846 , G06F9/544 , G06F12/0806 , G06F12/128
摘要： Systems and methods for writing and/or reading data to a point-to-point shared memory communication mechanism are provided according to embodiments disclosed herein. According to one embodiment, a determination may be made whether a first memory location in the cache of a general purpose multi-core processor includes an empty symbol. If the first memory location includes the empty symbol, then data may be placed in the first memory location in the cache. If the first memory location does not include the empty symbol, then waiting until it does. In another embodiment, a determination may be made whether a first memory location of a general purpose multi-core processor includes the empty symbol. If it does not, then data may be read from the first memory location and/or the empty symbol may be written into the first memory location. If the first memory location does include the empty symbol, then pausing.
摘要翻译：根据本文公开的实施例提供了用于将数据写入和/或读取到点对点共享存储器通信机制的系统和方法。根据一个实施例，可以确定通用多核处理器的高速缓存中的第一存储器位置是否包括空符号。如果第一存储器位置包括空符号，则数据可以被放置在高速缓存中的第一存储器位置中。如果第一个内存位置不包含空符号，则等待直到它为止。在另一个实施例中，可以确定通用多核处理器的第一存储器位置是否包括空符号。如果没有，则可以从第一存储器位置读取数据和/或空符号可以写入第一存储器位置。如果第一个内存位置确实包含空符号，则暂停。

3. 发明申请

US20080276056A1 Efficient Point-To-Point Enqueue And Dequeue Communications 有权
标题翻译：高效的点到点入队和出队通信
公开(公告)号：US20080276056A1
公开(公告)日：2008-11-06
申请号：US12106712
申请日：2008-04-21
申请人： John Giacomoni , Manish Vachharajani
发明人： John Giacomoni , Manish Vachharajani
IPC分类号： G06F12/00
CPC分类号： G06F12/0846 , G06F9/544 , G06F12/0806 , G06F12/128
摘要： Systems and methods for writing and/or reading data to a point-to-point shared memory communication mechanism are provided according to embodiments disclosed herein. According to one embodiment, a determination may be made whether a first memory location in the cache of a general purpose multi-core processor includes an empty symbol. If the first memory location includes the empty symbol, then data may be placed in the first memory location in the cache. If the first memory location does not include the empty symbol, then waiting until it does. In another embodiment, a determination may be made whether a first memory location of a general purpose multi-core processor includes the empty symbol. If it does not, then data may be read from the first memory location and/or the empty symbol may be written into the first memory location. If the first memory location does include the empty symbol, then pausing.
摘要翻译：根据本文公开的实施例提供了用于将数据写入和/或读取到点对点共享存储器通信机制的系统和方法。根据一个实施例，可以确定通用多核处理器的高速缓存中的第一存储器位置是否包括空符号。如果第一存储器位置包括空符号，则数据可以被放置在高速缓存中的第一存储器位置中。如果第一个内存位置不包含空符号，则等待直到它为止。在另一个实施例中，可以确定通用多核处理器的第一存储器位置是否包括空符号。如果没有，则可以从第一存储器位置读取数据和/或空符号可以写入第一存储器位置。如果第一个内存位置确实包含空符号，则暂停。

4. 发明授权

US08755378B2 Efficient pipeline parallelism using frame shared memory 有权
标题翻译：使用帧共享内存的高效管道并行性
公开(公告)号：US08755378B2
公开(公告)日：2014-06-17
申请号：US13590307
申请日：2012-08-21
申请人： John Giacomoni , Manish Veachharajani
发明人： John Giacomoni , Manish Veachharajani
IPC分类号： H04L12/28
CPC分类号： G06F12/0846 , G06F9/544 , G06F12/0806 , G06F12/128
摘要： A systems and methods are disclosed that provide an efficient parallel pipeline for data processing using a multi-core processor. Embodiments allocate a shared memory portion of the memory that is accessible from more than one context of execution and/or process a frame in a plurality of processing stages processed by a context of execution. In some embodiments, each of the plurality of processing stages may be bound to a processing core of the multi-core processor. In other embodiments include one or more processing stages with a point-to-point communication mechanism that operates in shared memory.
摘要翻译：公开了一种提供用于使用多核处理器的数据处理的有效的并行流水线的系统和方法。实施例分配存储器的共享存储器部分，其可由多于一个执行上下文访问和/或处理由执行上下文处理的多个处理阶段中的帧。在一些实施例中，多个处理级中的每一个可以被绑定到多核处理器的处理核心。在其他实施例中，包括具有在共享存储器中操作的点对点通信机制的一个或多个处理级。

5. 发明申请

US20090055627A1 Efficient Pipeline Parallelism Using Frame Shared Memory 有权
标题翻译：使用帧共享内存的高效管道并行性
公开(公告)号：US20090055627A1
公开(公告)日：2009-02-26
申请号：US12106684
申请日：2008-04-21
申请人： John Giacomoni , Manish Vachharajani
发明人： John Giacomoni , Manish Vachharajani
IPC分类号： G06F9/46 , G06F15/76 , G06F9/02
CPC分类号： G06F12/0846 , G06F9/544 , G06F12/0806 , G06F12/128
摘要： A systems and methods are disclosed that provide an efficient parallel pipeline for data processing using a multi-core processor. Embodiments allocate a shared memory portion of the memory that is accessible from more than one context of execution and/or process a frame in a plurality of processing stages processed by a context of execution. In some embodiments, each of the plurality of processing stages may be bound to a processing core of the multi-core processor. In other embodiments include one or more processing stages with a point-to-point communication mechanism that operates in shared memory.
摘要翻译：公开了一种提供用于使用多核处理器的数据处理的有效的并行流水线的系统和方法。实施例分配存储器的共享存储器部分，其可由多于一个执行上下文访问和/或处理由执行上下文处理的多个处理阶段中的帧。在一些实施例中，多个处理级中的每一个可以被绑定到多核处理器的处理核心。在其他实施例中，包括具有在共享存储器中操作的点对点通信机制的一个或多个处理级。

6. 发明授权

US08279865B2 Efficient pipeline parallelism using frame shared memory 有权
标题翻译：使用帧共享内存的高效管道并行性
公开(公告)号：US08279865B2
公开(公告)日：2012-10-02
申请号：US12106684
申请日：2008-04-21
申请人： John Giacomoni , Manish Vachharajani
发明人： John Giacomoni , Manish Vachharajani
IPC分类号： H04L12/28
CPC分类号： G06F12/0846 , G06F9/544 , G06F12/0806 , G06F12/128
摘要： A systems and methods are disclosed that provide an efficient parallel pipeline for data processing using a multi-core processor. Embodiments allocate a shared memory portion of the memory that is accessible from more than one context of execution and/or process a frame in a plurality of processing stages processed by a context of execution. In some embodiments, each of the plurality of processing stages may be bound to a processing core of the multi-core processor. In other embodiments include one or more processing stages with a point-to-point communication mechanism that operates in shared memory.
摘要翻译：公开了一种提供用于使用多核处理器的数据处理的有效的并行流水线的系统和方法。实施例分配存储器的共享存储器部分，其可由多于一个执行上下文访问和/或处理由执行上下文处理的多个处理阶段中的帧。在一些实施例中，多个处理级中的每一个可以被绑定到多核处理器的处理核心。在其他实施例中，包括具有在共享存储器中操作的点对点通信机制的一个或多个处理级。

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