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1. 发明授权

US07375662B2 Method of and system for performing differential lossless compression 有权
标题翻译：执行差分无损压缩的方法和系统
公开(公告)号：US07375662B2
公开(公告)日：2008-05-20
申请号：US10725008
申请日：2003-12-02
申请人： Sophie Wilson , John Redford
发明人： Sophie Wilson , John Redford
IPC分类号： H03M7/00
CPC分类号： H03M7/3088 , H03M7/30
摘要： A method of decompressing data words of an instruction set includes: A. filling a primary dictionary with at least one primary data word of the instruction set, each of the at least one primary data word being stored in the primary dictionary in a location associated with a distinct primary dictionary index; B. filling at least one secondary dictionary with at least one difference bit stream, each of the at least one difference bit stream being stored in one of the at least one secondary dictionary in a location associated with a distinct secondary dictionary index; C. receiving a code word, the code word comprising: a. a header which identifies the primary dictionary and a specific one of the at least one secondary dictionary; b. a first bit stream; and c. a second bit stream; wherein the first bit stream comprises the distinct primary dictionary index and the second bit stream comprises the distinct secondary dictionary index; D. retrieving the primary data word stored at the location in the primary dictionary location associated with the distinct primary dictionary index; E. retrieving the difference bit stream stored at the location in the at least one secondary dictionary location associated with the distinct secondary dictionary index; and F. performing a logic operation on the primary data word and the difference bit stream to obtain a resultant data word that is not stored in either the at least one primary dictionary or the at least one secondary dictionary.
摘要翻译：一种解压缩指令集的数据字的方法包括：A.用指令集的至少一个主数据字填充主字典，所述至少一个主数据字中的每一个都存储在与主字典相关联的位置中的主字典中一个独特的主要字典索引; B.用至少一个差分比特流填充至少一个辅助词典，所述至少一个差分比特流中的每一个存储在与不同次级词典索引相关联的位置中的所述至少一个辅助词典之一中; C.接收码字，码字包括：a。识别所述主字典和所述至少一个辅助字典中的特定一个的标题; b。第一位流; 和c。第二位流其中所述第一比特流包括所述不同的主词典索引，并且所述第二比特流包括所述不同的辅助词典索引; D.检索存储在与不同主词典索引相关联的主字典位置中的位置处的主数据字; E.检索存储在与所述不同次级词典索引相关联的所述至少一个辅助字典位置中的位置处的差异比特流; 以及F.对所述主数据字和所述差分比特流执行逻辑运算，以获得未被存储在所述至少一个主字典或所述至少一个辅助字典中的结果数据字。

2. 发明申请

US20050193384A1 Loader module, and method for loading program code into a memory 失效
标题翻译：装载器模块，以及将程序代码加载到存储器中的方法
公开(公告)号：US20050193384A1
公开(公告)日：2005-09-01
申请号：US10896053
申请日：2004-07-22
申请人： John Redford
发明人： John Redford
IPC分类号： G06F9/44 , G06F9/445
CPC分类号： G06F9/44521
摘要： A loader module for loading program code into a memory is described, whereby the memory may be partially defective, with non-defective parts of the memory being indicated by diagnostic information. The loader module is adapted for loading program code, in accordance with the diagnostic information, into non-defective parts of the memory, and for relinking the program code in accordance with the memory locations it has been loaded to. Furthermore, a method for loading program code into a memory is described. The method comprises the following steps which may be carried out in arbitrary order: loading program code, in accordance with diagnostic information, into non-defective parts of the memory, and relinking the program code in accordance with the memory locations it has been loaded to.
摘要翻译：描述用于将程序代码加载到存储器中的加载器模块，由此存储器可能是部分缺陷的，存储器的非缺陷部分由诊断信息指示。加载器模块适于将根据诊断信息的程序代码加载到存储器的无缺陷部分中，以及根据其加载到的存储器位置重新连接程序代码。此外，描述了将程序代码加载到存储器中的方法。该方法包括可以按任意顺序执行的以下步骤：根据诊断信息将程序代码加载到存储器的无缺陷部分，并根据其加载的存储器位置重新链接程序代码。

3. 发明授权

US06720894B2 Method of and system for performing differential lossless compression 失效
标题翻译：执行差分无损压缩的方法和系统
公开(公告)号：US06720894B2
公开(公告)日：2004-04-13
申请号：US10232728
申请日：2002-09-03
申请人： Sophie Wilson , John Redford
发明人： Sophie Wilson , John Redford
IPC分类号： H03M700
CPC分类号： H03M7/3088 , H03M7/30
摘要： A method of decompressing data words of an instruction set includes: A. filling a primary dictionary with at least one primary data word of the instruction set, each of the at least one primary data word being stored in the primary dictionary in a location associated with a distinct primary dictionary index; B. filling at least one secondary dictionary with at least one difference bit stream, each of the at least one difference bit stream being stored in one of the at least one secondary dictionary in a location associated with a distinct secondary dictionary index; C. receiving a code word, the code word comprising: a. a header which identifies the primary dictionary and a specific one of the at least one secondary dictionary; b. a first bit stream; and c. a second bit stream; wherein the first bit stream comprises the distinct primary dictionary index and the second bit stream comprises the distinct secondary dictionary index; D. retrieving the primary data word stored at the location in the primary dictionary location associated with the distinct primary dictionary index; E. retrieving the difference bit stream stored at the location in the at least one secondary dictionary location associated with the distinct secondary dictionary index; and F. performing a logic operation on the primary data word and the difference bit stream to obtain a resultant data word that is not stored in either the at least one primary dictionary or the at least one secondary dictionary.
摘要翻译：解压缩指令集的数据字的方法包括：A。用指令集的至少一个主数据字填充主字典，所述至少一个主数据字中的每一个在与不同主词典索引相关联的位置中存储在主词典中; B。用至少一个差分比特流填充至少一个辅助词典，所述至少一个差分比特流中的每一个存储在与不同次级词典索引相关联的位置中的至少一个辅助词典中的一个中; C。接收码字，码字包括：a。标识所述主字典和所述至少一个辅助字典中的特定一个的标题; b。第一位流; andc。第二比特流;其中所述第一比特流包括所述不同的主词典索引，所述第二比特流包括所述不同的辅助词典索引; D。检索存储在与不同主词典索引相关联的主字典位置中的位置处的主数据字; E。检索存储在与所述不同次级字典索引相关联的所述至少一个辅助字典位置中的所述位置处的差异比特流; 和F。对所述主数据字和所述差分比特流执行逻辑运算以获得未被存储在所述至少一个主词典或所述至少一个辅助词典中的结果数据字。

4. 发明授权

US06052703A Method and apparatus for determining discrete cosine transforms using matrix multiplication and modified booth encoding 失效
标题翻译：使用矩阵乘法和修改的摊位编码确定离散余弦变换的方法和装置
公开(公告)号：US06052703A
公开(公告)日：2000-04-18
申请号：US076521
申请日：1998-05-12
申请人： John Redford
发明人： John Redford
IPC分类号： G06F17/14
CPC分类号： G06F17/147
摘要： A method and apparatus for performing matrix multiplication used in image processing is described. A modified Booth encoding method is used to reduce the logic circuitry in processor modules used for calculating forward and inverse discrete cosine transforms. A set of products of image values and matrix coefficients are generated and provided to a set of multiplexers. The multiplexers provide preselected products to a set of accumulators. The accumulators combine the products to generate the set of transform coefficients at the accumulator outputs.
摘要翻译：描述用于在图像处理中使用的矩阵乘法的方法和装置。改进的布斯编码方法用于减少用于计算前向和反向离散余弦变换的处理器模块中的逻辑电路。产生一组图像值和矩阵系数的乘积并将其提供给一组多路复用器。多路复用器为一组蓄电池提供预选产品。累加器组合产品以在累加器输出端产生一组变换系数。

5. 发明申请

US20050273577A1 Microprocessor with integrated high speed memory 有权
标题翻译：具有集成高速存储器的微处理器
公开(公告)号：US20050273577A1
公开(公告)日：2005-12-08
申请号：US10857979
申请日：2004-06-02
申请人： Sophie Wilson , John Redford
发明人： Sophie Wilson , John Redford
IPC分类号： G06F9/345 , G06F9/38 , G06F9/40
CPC分类号： G06F9/30036 , G06F9/30043 , G06F9/3455
摘要： The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and memory components. Particularly, the present invention relates to a computer system with an processor architecture in which register addresses are generated with more than one execution channel controlled by one central processing unit with at least one load/store unit for loading and storing data objects, and at least one cache memory associated to the processor holding data objects accessed by the processor, wherein said processor's load/store unit contains a high speed memory directly interfacing said load/store unit to the cache. The present invention improves the of architectures with dual ported microprocessor implementations comprising two execution pipelines capable of two load/store data transactions per cycle. By including a cache memory inside the load/store unit, the processor is directly interfaced from its load/store units to the caches. Thus, the present invention accelerates data accesses and transactions from and to the load/store units of the processor and the data cache memory.
摘要翻译：本发明涉及（微）计算机设计和架构领域，特别涉及与（微）处理器和存储器组件之间移动数据值相关联的微体系结构。特别地，本发明涉及一种具有处理器结构的计算机系统，其中通过一个具有至少一个用于加载和存储数据对象的加载/存储单元的中央处理单元控制的多于一个执行通道生成寄存器地址，并且至少与处理器相关联的一个缓存存储器，其保存由处理器访问的数据对象，其中所述处理器的加载/存储单元包含将所述加载/存储单元直接连接到高速缓存的高速存储器。本发明改进了具有双端口微处理器实现的架构，其包括能够在每个周期进行两次加载/存储数据事务的两条执行管线。通过在加载/存储单元内部包括高速缓冲存储器，处理器从其加载/存储单元直接连接到高速缓存。因此，本发明加速了来自处理器和数据高速缓冲存储器的加载/存储单元的数据访问和事务。

6. 发明授权

US06931518B1 Branching around conditional processing if states of all single instruction multiple datapaths are disabled and the computer program is non-deterministic 失效
标题翻译：如果禁用所有单个指令多个数据路径的状态，并且计算机程序是非确定性的，则分支进行条件处理
公开(公告)号：US06931518B1
公开(公告)日：2005-08-16
申请号：US09724196
申请日：2000-11-28
申请人： John Redford
发明人： John Redford
IPC分类号： G06F9/44 , G06F15/00
CPC分类号： G06F8/45
摘要： A method of determining whether datapaths executing in a computer program should execute conditional processing block includes determining whether processor enable (PE) states of all of the datapaths are disabled, and branching around the conditional processing if the PE states of all of the datapaths are disabled. Branching is not performed, even if the PE states of all of the datapaths are disabled, if the program is determined to be deterministic. That determination is made by evaluating the state of a deterministic bit. Instructions are also provided for carrying out the determining and branching operations. The instructions may also be combined with operations that maintain the PE states during conditional processing.
摘要翻译：确定在计算机程序中执行的数据通路是否应执行条件处理块的方法包括确定是否禁用所有数据路径的处理器使能（PE）状态，以及如果所有数据路径的PE状态被禁用，则在条件处理之前分支。即使所有数据路径的PE状态被禁用，如果程序被确定为确定性，则不执行分支。该确定是通过评估确定性位的状态来进行的。还提供了执行确定和分支操作的说明。指令还可以与在条件处理期间维持PE状态的操作相结合。

7. 发明授权

US06211864B1 Method and apparatus for optimizing storage of compressed images in memory 有权
标题翻译：用于优化存储器中压缩图像的存储的方法和装置
公开(公告)号：US06211864B1
公开(公告)日：2001-04-03
申请号：US09505111
申请日：2000-02-16
申请人： John Redford
发明人： John Redford
IPC分类号： G09G500
CPC分类号： H04N19/182 , H04N19/115 , H04N19/137 , H04N19/146 , H04N19/15 , H04N19/176 , H04N19/60
摘要： A method and apparatus for optimizing the storage of compressed images includes serially storing pixel block data in memory. Fixed memory utilization can be improved for images having pixel blocks of varying information content. A cumulative memory allocation is updated during processing of each pixel block and compared with the current memory requirement. Memory not utilized for earlier processed pixel blocks having low information content can be used to store later processed high information content pixel blocks.
摘要翻译：用于优化压缩图像的存储的方法和装置包括将像素块数据串行存储在存储器中。对于具有不同信息内容的像素块的图像，可以改进固定的存储器利用率。在每个像素块的处理期间更新累积存储器分配并与当前存储器需求进行比较。不能用于具有低信息内容的较早处理的像素块的存储器可用于存储稍后处理的高信息内容像素块。

8. 发明授权

US07415654B2 Data integrity checking 失效
标题翻译：数据完整性检查
公开(公告)号：US07415654B2
公开(公告)日：2008-08-19
申请号：US10928961
申请日：2004-08-30
申请人： John Redford
发明人： John Redford
IPC分类号： G06F11/00 , G11C29/00
CPC分类号： G11C29/56
摘要： A tester unit for evaluating data integrity of a block of data is described. The tester unit comprises a checksum determination facility adapted for deriving a checksum value from a block of data stored in a memory, and a checksum evaluation facility adapted for comparing the derived checksum value with a predetermined checksum value, and for initiating a reload of the block in case the derived checksum value differs from the predetermined checksum value.
摘要翻译：描述用于评估数据块的数据完整性的测试器单元。测试器单元包括校验和确定设备，其适于从存储在存储器中的数据块导出校验和值，以及校验和评估设备，其适于将导出的校验和值与预定校验和值进行比较，并用于启动块的重新加载在导出的校验和值与预定校验和值不同的情况下。

9. 发明申请

US20050253858A1 Memory control system and method in which prefetch buffers are assigned uniquely to multiple burst streams 审中-公开
标题翻译：其中预取缓冲区被唯一地分配给多个突发流的存储器控制系统和方法
公开(公告)号：US20050253858A1
公开(公告)日：2005-11-17
申请号：US10846995
申请日：2004-05-14
申请人： Takahide Ohkami , John Redford
发明人： Takahide Ohkami , John Redford
IPC分类号： G06F12/08 , G06F12/14 , G06F13/16 , G09G5/39
CPC分类号： G06F13/1673 , G06F12/0862 , G06F2212/6022
摘要： In a prefetch buffering system and method, a pool of prefetch buffers are organized in such a manner that there is a tight connection between the buffer pool and the data streams of interest. In this manner, efficient prefetching of data from memory is achieved and the amount of required buffer space is reduced. A memory control system controls the reading of data from a memory. A plurality of buffers buffer data read from the memory. A buffer assignment unit assigns a plurality of data streams to the plurality of buffers. The buffer assignment unit assigns to each data stream a primary buffer and a secondary buffer of the plurality of buffers, such that upon receiving a data request from a first data stream, the primary buffer assigned to the first data stream contains fetch data of the data request and the secondary buffer assigned to the first data stream contains prefetch data of the data request.
摘要翻译：在预取缓冲系统和方法中，预取缓冲器池以这样的方式组织，使得缓冲池和感兴趣的数据流之间存在紧密的连接。以这种方式，实现了来自存储器的数据的有效预取，并且减少了所需的缓冲空间量。存储器控制系统控制从存储器读取数据。从存储器读取的多个缓冲器缓冲器数据。缓冲器分配单元将多个数据流分配给多个缓冲器。缓冲器分配单元向每个数据流分配多个缓冲器中的主缓冲器和次缓冲器，使得在从第一数据流接收到数据请求时，分配给第一数据流的主缓冲器包含数据的提取数据分配给第一数据流的请求和辅助缓冲器包含数据请求的预取数据。

10. 发明授权

US6130631A Method and apparatus utilizing a simplified content-addressable memory for JPEG decoding 失效
标题翻译：利用简化的内容寻址存储器进行JPEG解码的方法和装置
公开(公告)号：US6130631A
公开(公告)日：2000-10-10
申请号：US75603
申请日：1998-05-11
申请人： John Redford
发明人： John Redford
IPC分类号： G06T9/00 , H03M7/40
CPC分类号： G06T9/00
摘要： A method and apparatus for decoding of two part binary symbols, such as JPEG symbols, is disclosed. The invention takes advantage of the relationship between the Huffman symbol length, the magnitude length, and the overall symbol length so that none of these lengths need to be stored in memory. Using the invention, a Huffman symbol can be detected. Once the symbol is detected, the invention facilitates the determination of the Huffman symbol length, the magnitude length, and the overall symbol length.
摘要翻译：公开了一种用于对诸如JPEG符号之类的二部分二进制符号进行解码的方法和装置。本发明利用霍夫曼符号长度，幅度长度和整个符号长度之间的关系，使得这些长度不需要存储在存储器中。使用本发明，可以检测霍夫曼符号。一旦检测到符号，本发明有助于确定霍夫曼符号长度，幅度长度和整体符号长度。

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